Length : 4 days
Course Description
Universal Verification Methodology (UVM) is the IEEE1800.1 class-based verification library and reuse methodology for SystemVerilog. The UVM class library provides the basic building blocks for creating verification data and components. The UVM methodology enables engineers to quickly develop powerful, reusable, and scalable object-oriented verification environments.
This course teaches you UVM in exactly the same way as you would use the methodology in a real-life project. First we create data stimulus items, then we use the building blocks of the UVM class library to create a configurable, reusable UVM Verification Component (UVC) to drive the stimulus into a DUT. Then you learn how to combine multiple UVCs into a flexible, powerful verification environment with scoreboards and register models. The goal is to allow you to walk away from this course and immediately be effective in working on UVM projects.
This course covers UVM1.2, but can also be used for UVM1.1d. The differences between the two versions are minor and new UVM1.2 content is clearly labelled in the course.
This version of the class teaches a methodology compatible with hardware acceleration. See the video "Future-Proof Your UVM Environments with Acceleration Optimization" for more information.
For instuctor-led classes, this course is usually combined with Essential SystemVerilog for UVM.
Learning Objectives
After completing this course, you will be able to:
- Understand the features and capabilities of the UVM class library for SystemVerilog
- Create and configure reusable, scalable, and robust UVM Verification Components (UVCs)
- Combine multiple UVCs into a complete verification environment
- Integrate scoreboards, multichannel sequencers and Register Models
Software Used in This Course
- Incisive Enterprise Simulator XL
- Xcelium
Software Release(s)
INCISIVE161, XCELIUM1903
Modules in this Course
Days 1-3– Section1: Core UVM Verification Environment
- Introduction to UVM Methodology and Universal Verification Component (UVC) Structure
- Overview of the Router Lab Project
- Stimulus Modeling
- Declaring data items
- Field automatio and data operations (copy, clone, print, etc.)
- Simulation Phases
- Standard and run-time phasing
- Test and Testbench Classes
- Testbench layer
- Test and test selection
- Reports
- Creating a Simple Environment
- UVM component classes
- Structure of a simple environment
- Packaging and directory structures
- Configuration
- Configuration database (uvm_config_db)
- How configuration works, with rules, examples and debugging
- set_config method calls (deprecated in UVM1.2)
- Type Overrides and the Factory
- Constraint layering and behavior modification
- Factories
- Type and instance overrides
- UVM Sequences
- Sequence structure
- uvm_do macros
- Alternatives to uvm_do macros
- Nested sequences and sequence properties
- Sequence selection
- Objection mechanism for stopping simulation
- Objection changes in UVM1.2
- Connecting to a DUT
- Virtual SystemVerilog interfaces
- Assigning interfaces using the configuration database
- Interface and Module UVCs
- Integrating multiple UVCs
- UVCs with multiple agents
- Configuration objects
- Multichannel Sequences (virtual sequences)
- Virtual sequencers
- Defining virtual sequences
- Building a Scoreboard
- Scoreboard requirements and considerations
- Connecting components with TLM analysis interfaces
- Hierarchical connections with export
Day 4 – Section 3: Further UVM
- Transaction-Level Modeling (TLM)
- Concepts and terminology
- Simple, unidirectional connections (put, get, peek)
- TLM FIFO
- Scoreboards with TLM analysis FIFO
- TLM2
- Functional Coverage Modeling (Optional)
- Coverage-driven verification overview
- Coverage considerations in a UVC
- Introduction to Register Modeling
- Overview of the purpose and structure of register modeling
- Generation of a register model
- Integration into an environment
- Simulation using built-in and user-defined register sequences
- Conclusions
Lab Exercises
Lab exercises are structured around the verification of a real-life router design. The lab sessions include:
- Creating simple data stimulus
- Universal Verification Component (UVC) architecture
- Factories and configuration control
- Sequences
- Integrating multiple UVCs
- Writing multichannel and system-level tests
- Building a scoreboard
- Functional coverage
- Register modeling of a standalone design
Audience
- Design engineers
- Verification engineers
Prerequisites
You must have experience with or knowledge of the SystemVerilog Language, specifially:
- Declaration and use of SystemVerilog class instances
- Static methods and properties
- Inheritance and composite classes
- Randomization and constraint of class properties
Or you must have completed one of the following courses:
Related Courses
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
Free Online Training Bytes (Videos)
Course ID: 86070
