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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Integrity 3D-IC Platform
          • Cadence Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Voltus IC Power Integrity Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
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          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
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          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • 112G/56G SerDes
          • Chiplet and D2D
          • Denali Memory Interface and Storage IP
          • Interface IP
          • PCIe and CXL
          • Tensilica Processor IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
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          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
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          • System Analysis Resources Hub
          • AWR Free Trial
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          • Library and Design Data Management
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          • Augmented Reality Lab Tools
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  • Tensilica Xtensa LX Processor Fundamentals



Tensilica Xtensa LX Processor Fundamentals

Online Courses
Version Region
9.6 Online ENROLL
Other Versions Online EXPRESS INTERESTINQUIRE

Length: 2 days (16 Hours)

Course Description

This course covers the fundamentals of Tensilica® Xtensa® LX processor architecture and configuration options, software tools, programming, optimization and debug. 

You will explore topics in processor architecture and the configurable options of the Xtensa® LX series processors. You will practice working with the Xplorer Integrated Development Environment (IDE), working with Tensilica software tools, and programming Xtensa processors in the labs that are part of this course. You also learn to program Xtensa processors with application-specific instructions added by using the Tensilica Instruction Extension (TIE) language.Emulation of a Tensilica processor is discussed and demonstrated. 

The solid fundamentals taught in this course enable you to quickly become productive in the use of Xtensa LX processors for your SoC design.

Learning Objectives

After completing this course, you will be able to:

  • Use Xtensa Xplorer (IDE) for software development
  • Write, optimize, and debug C/C++ code for any Xtensa processor core
  • Understand Xtensa LX processor architecture features and their impact on performance
  • Configure an Xtensa LX processor suitable for your application
  • Customize your application’s memory map to match your target system
  • Program Xtensa LX processors that have TIE extensions
  • Emulate and debug Xtensa processor on an FPGA or other emulation platform

Software Used in This Course

  • Xtensa Software Tools Release RI-2021.6

Software Release(s)

RI-2021.6

Modules in this Course

Tensilica Processor Architecture

  • Xtensa LX Processor Architecture Basics
  • AR Register File and the Application Binary Interface
  • Xtensa-Specific Local Memory Architecture
  • Xtensa-Specific System Memory Interface
  • Xtensa TIE Interfaces
  • Xtensa Exception and Interrupt Architecture

Programming Cores with Tensilica Instruction Extensions

  • Introduction to Tensilica Instruction Extensions
  • Writing C/C++ Code for Instruction Extensions
  • Understanding Compiled Code
  • Simulating C/C++ Code with TIE

Developing Software for Xtensa Processors

  • Introducing Xtensa Xplorer
    Lab: Installation and licensing; getting help and information; a first program
  • Working with Projects and Build Targets
    Lab: Creating projects; the active set; running your program
  • Running and Profiling with Xplorer
    Lab: Installing sample code; perspectives; build targets; profiling
  • Debugging your Code
    Lab: Debugging your code
  • Command-Line Environment
    Lab: Command lines; compiling, running, debugging and profiling your application
  • Introduction to Linker Support Packages
  • LSP Advanced Topics
  • Lab: Memory maps; identifying sections; modifying a memory map; moving stack/heap
  • Xtensa LX Exceptions and Interrupts
  • Lab: Understanding interrupt and timer code; writing the main function; compiling and simulating
  • XTOS and HAL
    Lab: Programming the MPU memory map; generating a bootstrap map

Xtensa Debug & Trace

  • Building Target Software for Real Hardware
  • Configuration Options for Hardware Debug and Trace
  • Single and Multiple-Core Debug Session Demonstrations

Audience

  • SoC architects designing systems with Xtensa processors
  • Architects/Designers configuring Xtensa processors for a specific application
  • Software developers programming Xtensa processors
  • Other software/hardware engineers working extensively with Xtensa processors

Prerequisites

You must have experience with or knowledge of the following:

  • Basic microprocessor architecture
  • Programming in C/C++

Related Courses

  •  Tensilica Instruction Extension (TIE) Language and Design

Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.

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Course ID: 86037

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“The course met my expectations. A practical course on implementing the physical prototype of a Tensilica Processor in an FPGA board. The support is good and it is easy to enroll and access the courses.”

Jones M.A. Da Silva, Ruhr University Bochum

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