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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Integrity 3D-IC Platform
          • Cadence Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Voltus IC Power Integrity Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • 112G/56G SerDes
          • Chiplet and D2D
          • Denali Memory Interface and Storage IP
          • Interface IP
          • PCIe and CXL
          • Tensilica Processor IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
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      • PCB Design and Analysis
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          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • Allegro X Design Platform
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  • Virtuoso Layout Pro: T5 Interactive Routing (XL)



Virtuoso Layout Pro: T5 Interactive Routing (XL)

Online Courses
Instructor-Led Schedule
Date Version Country Location
27 Jun 2022 IC6.1.8/ICADVM 18.1/ICADVM 20.1 Germany EMEA-Blended-Germany
Germany
ENROLL
27 Jun 2022 IC6.1.8/ICADVM 18.1/ICADVM 20.1 United Kingdom Of Great Britain And Northern Ireland EMEA-Blended-UK
United Kingdom Of Great Britain And Northern Ireland
ENROLL
23 Sep 2022 IC6.1.8/ICADVM 18.1/ICADVM 20.1 Sweden Kista-Stockholm
Sweden
ENROLL
23 Sep 2022 IC6.1.8/ICADVM 18.1/ICADVM 20.1 United Kingdom Of Great Britain And Northern Ireland Bracknell-London
United Kingdom Of Great Britain And Northern Ireland
ENROLL
11 Oct 2022 IC6.1.8/ICADVM 18.1/ICADVM 20.1 Germany Feldkirchen-Munich
Germany
ENROLL
08 Dec 2022 IC6.1.8/ICADVM 18.1/ICADVM 20.1 Israel Petah-Tikva-Tel Aviv
Israel
ENROLL
Scheduled upon demandOn demand EXPRESS INTERESTINQUIRE
Version Region
IC6.1.8/ICADVM 18.1/ICADVM 20.1 Online ENROLL
IC6.1.7 Online ENROLL
Other Versions Online EXPRESS INTERESTINQUIRE

Length: 1 day (8 Hours)

Digital Badge Available

Course Description

In this course, you explore the techniques to increase your productivity using all the assisted features in the Create Wire family of commands in Virtuoso® Layout Suite XL. You use the different degrees of automation to route wires using the existing connectivity information. You use the smart auto via feature and explore the Show Preview and Show Hints options.

The following videos for this course include:

Auto Merging Wires during Interactive Routing – Overview

Allowing Loops during Interactive Routing – Overview

Adjusting Edited Vias Params – Overview

Showing Alignment Markers during Interactive Routing – Overview

NOTE: This course is compatible with IC 6.1.8, ICADVM 20.1

Learning Objectives

After completing this course, you will be able to:

  • Analyze the basic concepts and settings in wire creation
  • Create and modify the wires
  • Use the assisted wires creation
  • Use the smart auto via feature (Appendix)

Software Used in This Course

  • Virtuoso Schematic Editor XL
  • Virtuoso Layout Suite XL

Software Release(s)

IC 6.1.8, ICADVM 20.1

Modules in this Course

  • Basic Concepts and Settings in Wire Creation
  • Creating and Modifying Wires
  • Assisted Wires Creation
  • Smart Auto Via (Appendix) 

Audience

  • Layout Design Engineers
  • Layout CAD Managers
  • IC Designers
  • Analog/Mixed-Signal IC Designers
  • Analog IC Designers
  • Custom Circuit Designers
  • Chip Designers

Prerequisites

You must have:

  • Experience with layout design
  • Knowledge of schematic symbols and MOS devices
  • A basic knowledge of UNIX/Linux

Or you must have completed the following courses:

  • Virtuoso Layout Pro: T1 Environment and Basic Commands (L)
  • Virtuoso Layout Pro: T2 Create and Edit Commands (L)
  • Virtuoso Layout Pro: T3 Basic Commands (XL)
  • Virtuoso Layout Pro: T4 Advanced Commands (XL)

Related Courses

  • Virtuoso Layout Pro: T1 Environment and Basic Commands (L)
  • Virtuoso Layout Pro: T2 Create and Edit Commands (L)
  • Virtuoso Layout Pro: T3 Basic Commands (XL)
  • Virtuoso Layout Pro: T4 Advanced Commands (XL)
  • Virtuoso Layout Pro: T6 Constraint-Driven Flow and Power Routing
  • Virtuoso Layout Pro: T7 Module Generator and Floorplanner (XL/GXL)
  • Virtuoso Layout Pro: T8 Debugging Layout Issues
  • Virtuoso Layout Pro: T9 Virtuoso Design Planner

Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.

Free Online Training Bytes (Videos)

Course ID: 85091

Know How to Build the Perfect Layout: Cadence Virtuoso Layout Pro Training Series

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"Virtuoso Layout Pro is improving the well-known available tools and is introducing new powerful features that allow to increase the productivity in the daily work by decreasing time and effort."

Paolo F. Pino, NXP Semiconductors

“Very good training, fits my needs in short timeframe.”

Frederic Duez, STMicroelectronics

“Within our internal training analysis the customized Virtuoso Layout Pro training has reached the best score since 2003!!”

Andre Vullhorst, NXP Semiconductors

"Instructor gave real world demo which was very helpful."

Jacqueline Gaffney, Skyworks Solutions Inc.

“Very profitable course with professional, competent trainer”

Daniel Neustifter, Infineon Technologies

"Very good as a refresher for those who already have worked with Virtuoso in IC6.1."

Alexander Mora Sanchez, NXP Semiconductors

“Great trainer. (...) Very good atmosphere, good course; learned some new features and also old features that not have been used previously.”

 
 

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