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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Virtuoso RF Solution
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          • Virtuoso ADE Product Suite
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          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • System Design and Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation
          • Formal and Static Verification
          • FPGA-Based Prototyping
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Z1 Enterprise Emulation Platform
          • Protium X1 Enterprise Prototyping Platform
          • System VIP
          • RESOURCES
          • Flows
      • IP
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          • Interface IP
          • Denali Memory IP
          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
          • Verification IP
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
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        • PRODUCT CATEGORIES
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Sigrity Advanced SI
          • Sigrity Advanced PI
          • RESOURCES
          • System Analysis Resources Hub
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          • PCB Layout
          • Library and Design Data Management
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          • Augmented Reality Lab Tools
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          • Allegro PCB Designer
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  • Virtuoso Layout Pro: T4 Advanced Commands (XL)



Virtuoso Layout Pro: T4 Advanced Commands (XL)

Online Courses
Instructor-Led Schedule
Date Version Country Location
10 Mar 2021 IC6.1.8/ICADVM18.1 Israel EMEA-Blended-Israel
Israel
ENROLL
04 Jun 2021 IC6.1.8/ICADVM18.1 France Vélizy-Paris
France
ENROLL
10 Jun 2021 IC6.1.8/ICADVM18.1 Germany EMEA-Blended-Germany
Germany
ENROLL
Scheduled upon demandOn demand EXPRESS INTERESTINQUIRE
Version Region
IC6.1.8 Online ENROLL
IC6.1.7 Online ENROLL
Other Versions Online EXPRESS INTERESTINQUIRE

Length : 1 day

Digital Badge Available

Course Description

In this course, you analyze how to generate clones as free objects, grouped objects, and synchronized family. You use the synchronous copy feature, generate clones from modgen generate mutant clones, and analyze how to effectively reuse existing structures in your layout by using clone and copy. You create layout structures using the features of Generate Clones and Synchronous copy options. You update your layout after an Engineering Change Order (ECO) and update the layout to reflect the pin name changes between schematic and layout by using the Update Components and Nets (UCN) command.

View the videos available in the course in the links given below:

How to Generate Clones as Free Objects

How to Generate Clones as Grouped Objects

How to Generate Clones as Synchronized Family

How to Generate Synchronous Copy Clones of Wires and Examine its Synchronous Behavior

How to Generate Synchronous Copy Clones of Modgen and Examine its Synchronous Behavior

How to Generate Mutant Clones with Exact Connectivity turned ON / OFF with Relax Match Options

How to Update the Net and the Pin Names and Implement the Schematic Changes in the Layout

Learning Objectives

After completing this course, you will be able to:

  • Generate Clones as Free Objects, Grouped Objects, and Synchronized Family
  • Generate Synchronous Copy Clones of Wires
  • Examine Synchronous Behavior in the Synchronous Copy Clones of Wires Created by the Copy Command
  • Generate Synchronous Copy Clones of Modgen
  • Examine Synchronous Behavior in the Synchronous Copy Clones of Modgen Created by the Copy Command
  • Generate Mutant Clones with Exact Connectivity turned ON / OFF with Relax Match Options
  • Create a Repetitive Layout Cell Using the Clone and the Copy Commands
  • Implement an Engineering Change Order (ECO)
  • Update the Net and the Pin Names

Software Used in This Course

  • Virtuoso Layout Suite XL

Software Release(s)

IC 6.1.8, ICADVM18.1

Modules in this Course

  • Generating Clones
  • Updating Connectivity and Nets

Audience

  • Layout Design Engineers
  • Layout CAD Managers
  • IC Designers
  • Analog/Mixed-Signal IC Designers
  • Analog IC Designers
  • Custom Circuit Designers
  • Chip Designers

Prerequisites

You must have:

  • Experience with layout design
  • Knowledge of schematic symbols and MOS devices
  • A basic knowledge of UNIX/Linux

Or you must have completed the following courses:

  • Virtuoso Layout Pro: T1 Environment and Basic Commands (L)
  • Virtuoso Layout Pro: T2 Create and Edit Commands (L)
  • Virtuoso Layout Pro: T3 Basic Commands (XL)

Please note that some of the training features will require loading a set of SKILL files. It is recommended to include these files in your standard Virtuoso settings.

Course ID: 85090

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“Thank you very much for this excellent training. This training significantly improved our group layout tools understanding and capabilities. It was much more than I expected from this training!”

Mark Rozental, Motorola Solutions

"Virtuoso Layout Pro is improving the well-known available tools and is introducing new powerful features that allow to increase the productivity in the daily work by decreasing time and effort."

Paolo F. Pino, NXP Semiconductors

“Very good training, fits my needs in short timeframe.”

Frederic Duez, STMicroelectronics

“Within our internal training analysis the customized Virtuoso Layout Pro training has reached the best score since 2003!!”

Andre Vullhorst, NXP Semiconductors

"Instructor gave real world demo which was very helpful."

Jacqueline Gaffney, Skyworks Solutions Inc.

"Very good as a refresher for those who already have worked with Virtuoso in IC6.1."

Alexander Mora Sanchez, NXP Semiconductors

“You can’t present the material for a Layout Engineer any more clearly than this.”

Wolfgang Feldbaumer, ams AG

 
 

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