Length : 1 day
Course Description
This course focuses on the basic concepts required to work with Virtuoso® Layout Suite XL to create a layout using a connectivity-driven flow. You start with the creation and placement of your layout building blocks using manual and automated methods. You will learn about the Binder/Extractor, and also learn how to debug problems in the design connectivity. You will become familiar with Constraint Groups and learn how they affect your layout work.
Learning Objectives
After completing this course, you will be able to:
- Use Virtuoso Layout Suite (LS) XL to create a new layout cell from scratch
- Debug and address connectivity errors in your layout design
- Analyze how the Layout-XL binder and extractor work
- Describe how the Constraint Groups affect working with VLS-XL
Software Used in This Course
- Virtuoso Layout Suite XL/GXL
Software Release(s)
IC 6.1.8
Modules in this Course
- Design Creation and Placement
- Binder and Extractor
- Using Constraint Groups in Virtuoso
Audience
- Layout Design Engineers
- Layout CAD Managers
- IC Designers
- Analog/Mixed-Signal IC Designers
- Analog IC Designers
- Custom Circuit Designers
- Chip Designers
Prerequisites
You must have:
- Experience with layout design
- Knowledge of schematic symbols and MOS devices
- A basic knowledge of UNIX/Linux
Or you must have completed the following courses:
Related Courses
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
