Length: 2 Days (16 hours)
Become Cadence Certified
Course Description
This is an Engineer Explorer series course. The Engineer Explorer courses explore advanced topics.
This training provides an introduction to the concepts, challenges, and techniques for simulating and verifying low-power designs. It discusses how to communicate your design's low-power features to the simulator and downstream tools with the IEEE Std 1801™ Unified Power Format (UPF). It highlights the power-aware features of the Xcelium™ simulator.
Learning Objectives
After completing this course, you will be able to:
- Use Xcelium simulation to verify power control design elements
Software Used in This Course
- XLM300 [Version: 22.09] Xcelium Single-Core
Software Release(s)
XCELIUM 22.09
Modules in this Course
- Introduction to Low-Power Simulation
- Introduction to the IEEE Std 1801 Unified Power Format (UPF)
- Simulating a UPF-Based Low-Power RTL Design
- Adding Power States to Your UPF-Based Power Simulation
- Liberty File Support in Xcelium 22.03
- Instantiating Low-Power Design IP
- Textually Examining Power-Related Simulation Behavior with Tcl
- Graphically Examining Power-Related Simulation Behavior with the SimVision GUI
- Using Indago for Digital Low-Power Simulations
Audience
- Verification personnel using digital simulation to verify low-power designs
Prerequisites
You must have experience with or knowledge of the following:
- Using the Xcelium simulator to simulate and debug digital designs
- (Optional) Basics of Low-Power CMOS Design
Related Courses
- Xcelium Simulator
- Low-Power Synthesis Flow with Genus Synthesis Solution
- Conformal Low-Power Verification
Click here to view course learning maps, and here for complete course catalogs.
Course ID: 85080
