Physical Verification Language Rules Writer

Length : 2 days

Course Description

In this course, you learn the basic rules and syntax used for coding Physical Verification Language (PVL) rule decks. These include commands for inputs, output, runset structures, coloring etc. with the corresponding syntax and examples.

After completing this course, you will be able to:

• Get an overview of PVS products and setup
• Set up and run PVS in GUI and batch modes
• Set up, run and debug PVS–DRC
• Set up, run and debug PVS–LVS
• Examine the inputs to PVS and outputs from PVS
• Check the PVS Rule Files coded in PVL
• Analyze Tcl support in PVS
• Examine the PVL data storage mechanism
• Define the layers and create intermediate and derived layers
• Use Boolean operators
• Select polygons and edges based on various criteria
• Use the Sizing and Layer Generation commands
• Review "hierarchy manipulation" and "checking input data integrity" in PVL
• Explore how PVS Layer Viewer works as a PVL Debugger
• Measure the distance between Internal, External and Enclosure edges of polygons
• Examine Common Constraints and Arguments in PVL
• Explore Output options in PVL, in both edge and region formats
• Create sample DRC Rule Decks
• Check Antenna & Density in specific window area
• Select specific rules and create a DRC Summary File
• Explore a few PVL commands sourced by the DFM Engine
• Add, define, overwrite, port and attach Texts in Layout
• Locate soft-connect and Text short violations in PVS-LVS
• Define Virtual Connect and Incremental Connectivity
• Compute properties such as area, count, perimeter etc. 
• Extract properties such as location, string value of a text, net ID etc.
• Extract devices like MOS, Bipolar, Resistor, Capacitor, Diode etc.
• Examine PVL commands that creates data for Parasitic Extraction
• Perform ERC check by flagging Nets with Valid Path to other Nets or PG
• Promote user-named devices to standard devices
• Create an LVS report
• Explore H-Cell settings
• Check the filtering options in LVS
• Reduce devices by merging those connected in parallel or series
• Compare LVS parameters
• Check Virtuoso^® Layouts in Advanced Nodes
• Create & Model Edge Pairs Files
• Create Link Layers
• Divide a layer into two/three/multi output layers of different colors
• Check rule decks to report Double/Triple/Multi Patterning errors
• Perform balanced color distribution with density considerations
• Check color conflict of layers
• Fix DPT violations
• Find out the licenses required for PVL Coloring rules.
• Explore aucdl, aulvs and Create CDL settings in PVS–LVS and compare netlists
• Use an existing CDL file for PVS–LVS run
• Handle X and define prefix in the source netlists
• Modify netlisting options using the .simrc file

Software Used in This Course

• PVS161
• IC617
• ICADV123

Software Release(s)

PVS161, IC617, ICADV123

Modules in this Course

• Introduction to Physical Verification System (PVS)
• Layer Processing
• DRC Rules
• Layout Extraction
• ERC and LVS Rules
• Schematic Netlisting
• Preparation for PVS-QuantusFlow
• PVS Configurator
• LVS Debugging Tips

Audience

• CAD or PDK engineers who write the PVS rule decks/files

Prerequisites

You must have knowledge of the following:

• Familiarity with process rules and physical layout design
• Comfortable writing code that lets you discover design rules violations
• Verification tools (e.g., PVS) to demonstrate rule decks

Related Courses

• Physical Verification System
• Virtuoso Layout Design Basics
• Virtuoso Schematic Editor
• Using Virtuoso Constraints Effectively
• Assura Rules Writer
• Quantus QRC Transistor-Level T1: Overview and Technology Setup