Physical Verification Language Rules Writer

Length: 2 days

Course Description

In this course, you learn the basic rules and syntax used for coding Physical Verification Language (PVL) rule decks. These include commands for inputs, output, runset structures, coloring etc. with the corresponding syntax and examples.

Learning Objectives

After completing this course, you will be able to:

• Examine PVL data storage mechanism
• Define the layers and create intermediate and derived layers
• Use Boolean operators
• Select polygons and edges based on various criteria
• Use the sizing and layer generation commands
• Review "hierarchy manipulation" and "checking Input data integrity" in PVL
• Check how PVS/ Pegasus^™ Layer Viewer works as a PVL Debugger
• Explore PVL commands sourced by the DFM Engine
• Review the structure of PVS/Pegasus Rule Decks
• Measure the distance between internal, external or enclosure edges of polygons
• Examine common constraints and arguments in PVL
• Explore Output options in PVL, in both edge and region formats
• Create sample DRC rule decks
• Check Antenna and Density in a specific window area
• Select specific rules and create a DRC Summary file
• Add, define, overwrite, port and attach texts in the layout
• Locate soft-connect and text short violations in the PVS/Pegasus-LVS
• Define Virtual Connect and Incremental Connectivity
• Compute properties such as area, count, perimeter etc. 
• Extract properties such as location, the string value of a text, net ID etc.
• Extract devices like MOS, bipolar, resistor, capacitor, diode etc.
• Examine the PVL commands that create data for Parasitic Extraction
• Use pvtcl translator to convert PVL codes to faster TCL format
• Perform ERC check by flagging Nets with Valid Path to other Nets or PG
• Promote user-named devices to standard devices
• Create LVS report
• Explore H-Cell Settings
• Check filtering options in LVS
• Reduce devices by merging those connected in parallel or series
• Compare LVS parameters
• Explore aucdl, aulvs and create CDL settings in the PVS/Pegasus-LVS and compare netlists
• Use an existing CDL File for the PVS/Pegasus-LVS run
• Handle X and define prefix in the source netlists
• Modify netlisting options using .simrc file
• Get an overview of PVS/Pegasus products and setup
• Set up and run PVS/Pegasus in GUI and batch modes
• Examine the inputs to PVS/Pegasus and outputs from PVS/Pegasus
• Create and model edge pairs files
• Create Link Layers
• Divide a layer into two/three/Multi-output layers of different colors
• Check rule decks to report Double/Tri/Multi Patterning errors
• Perform Balanced color distribution with density considerations
• Check color conflict of layers
• Fix DPT violations
• Find out the licenses required for the PVL Coloring rules
• Identify LVS mismatch cases:
• Correct LVS comparison rule setup issues
• Set up a PVS/Pegasus-Quantus™ extracted view flow using utilities
• Add files needed to control SPICE and xDSPF output
• Set up the PVS/Pegasus-Quantus Technology directory

Software Used in This Course

• PEGASUS211
• ICADVM201

Software Release(s)

PEGASUS211, ICADVM201

Modules in this Course

• Modules
  • Layer Processing
  • DRC Rules
  • Layout Extraction
  • ERC and LVS Rules
  • Schematic Netlisting
• Appendices
  • Introduction to PVS/Pegasus
  • Coloring Rules
  • PVS/Pegasus LVS Debugging Tips
  • Preparation for PVS/Pegasus-Quantus Flow

Audience

• CAD or PDK engineers who write the PVS/Pegasus rule decks/files

Prerequisites

You must have knowledge of the following:

• Familiarity with process rules and physical layout design
• Comfortable writing code that lets you discover design rules violations
• Verification tools (for example, PVS, Pegasus) to demonstrate rule decks

Related Courses

• Pegasus Verification System
• Physical Verification System
• Virtuoso Layout Design Basics
• Virtuoso Schematic Editor
• Assura^® Rules Writer
• Quantus QRC Transistor-Level T1: Overview and Technology Setup

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