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  • China - 简体中文
  • Japan - 日本語
  • Korea - 한국어
  • Taiwan - 繁體中文
  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Integrity 3D-IC Platform
          • Cadence Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Voltus IC Power Integrity Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • 112G/56G SerDes
          • Chiplet and D2D
          • Denali Memory Interface and Storage IP
          • Interface IP
          • PCIe and CXL
          • Tensilica Processor IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • Allegro X Design Platform
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
      • Computational Fluid Dynamics
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
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        • Arm-Based Solutions
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        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
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        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
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        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
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  • Virtuoso Layout for Advanced Nodes



Virtuoso Layout for Advanced Nodes

Online Courses
Instructor-Led Schedule
Date Version Country Location
Scheduled upon demandOn demand EXPRESS INTERESTINQUIRE
Version Region
ICADV12.2 Online ENROLL
Other Versions Online EXPRESS INTERESTINQUIRE

Length: 2 days (16 Hours)

Course Description

Increased demand for faster, smaller, low-power chips continues to drive geometry shrinkage as one of the ways to manage the low-power, higher performance goals in smaller form factor. 40 nm chips are state-of-the-art, 32 nm and 28 nm designs are right around the corner, and companies are already planning for 20 nm (and below) flows, methodologies, and products. While these advanced process nodes promise tremendous advantages in power, performance, and design capacity, it also raises tough design challenges. These challenges include increased timing and power variability, complex layout rules, and incredibly large designs with massive amounts of IP.

A major new challenge at 20 nm (and below) is the requirement for extra masks (double patterning) to make existing lithography work at this advanced process node. Escalating data volume and denser, more complex chips are testing the limits of traditional routing architectures. Even the slightest perturbations in the design flow can cause dramatic swings in design integrity. Design teams face a predictability crisis riddled with silicon failures, performance degradation, and prolonged design schedules. And new process and design innovations, such as high-k metal gate, SOI, and 3-D packaging, are intensifying the pressures of adoption and rapid deployment.

This course takes designers through the back-end tools required to do 20 nm and below physical design, including a review of the 20 nm process and technology requirements, Multiple Patterning (MPT), wiring setup, variations of editing path segments using Create Wire, and Create Bus, streaming in/out Precolored data, device placement constraints with respect to dummy devices, diffusion rules, Track Patterns and Constraint Overrides.

The majority of this course is captured in embedded videos (25) and reflects the lab document for students who wish to either watch the videos, and/or go through the labs to reinforce what they learned from watching the videos.

Learning Objectives

After completing this course, you will be able to:

  • Understand and meet the requirements for setting up and creating physical designs using ICADV 12.2 software at 20nm and below.

Software Used in This Course

  • ICADV 12.2
  • IC 6.1.7

Software Release(s)

ICADV 12.2 and above

Modules in this Course

  • Advanced Node Technology Overview
  • FinFET Grids, Snap Patterns, Placement, and Abutment
  • VXL Layout Generation
  • MPT Introduction
  • Color Verification
  • Advanced Node Constraints
  • Width Space Patterns (WSP)

Audience

  • Physical Designers
  • Layout Engineers

Prerequisites

You must have experience with or knowledge of the following:

  • Virtuoso Layout Suites XL and GXL

Or you must have completed the following courses:

  • Virtuoso Connectivity-Driven Layout

Related Courses

  • Using Virtuoso Constraints Effectively

Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.

Course ID: 85066

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