Course Description
This course, covers modeling, simulation and analysis of power-aware parallel bus system (DDR3 and DDR4) using the Allegro Sigrity SystemSI - PBA II.
This course, on day one, covers modeling, simulation andanalysis of simple DDR3 and DDR4 parallel bus systems (DDR3-SPBS and DDR4-SPBS),without power distribution network. Based on lecture and hands-on labs in Module2, you will build block-level topologies of DDR3-SPBS and DDR4-SPBS, assign power-awareIBIS models to the controller and memory block, generate W-element transmissionline models to represent pre-payout DDR3 and DDR4 parallel bus interface andassign ideal transmission line model to the tuning block. You will generate a W-elementtransmission line model to represent the DDR3-pre-layout, using the built-inTLine editor. You will modify default names of the pins under the connectionports in the MCP section of this W-element model, in order to facilitate itsconnections to other blocks. Next, you will generate the W-element transmissionline model to represent the DDR4 interface, with the same modified MCP section.You will set up timing budget and analysis options for the DDR3-SPBS, includingchannel simulation options for the DDR4-SPBS. Next, you will simulate DDR4-SPBSand DDR3-SPBS, with/without on-die parasitics, package parasitics and sweeping othercircuit parameters. Based on these simulations, you will generate reports withtables and waveforms (2D plots, eye diagrams, BER eye, Bathtub plots, impulseresponse etc.). You will analyze these waveforms and tables with key signalquality and timing parameters to evaluate the signal integrity performance ofthe DDR3-SPBS and DDR4-SPBS.
On day two, this course covers modeling, simulation and analysisof power-aware DDR3 and DDR4 parallel bus systems (DDR3-PAPBS and DDR4-PAPBS) withpower distribution network. Based on lecture and hands-on labs in Module 3, youwill build DDR3-PAPBS and DDR4-PAPBS by modifying the DDR3-SPBS and DDR4-SPBS,respectively. You will assign the PowerSI generated S-Parameters model of thepower-aware parallel bus interface of a real-world PCB to the PCB block of theDDR3-PAPBS and DDR4-PAPBS. You will set up timing budget and analysis optionsfor the DDR3-PAPBS, including channel simulation options for the DDR4-PAPBS.Next, you will simulate DDR3-PAPBS with ideal/non-ideal power, with/without on-dieparasitics, package parasitics and sweeping other parameters (such as stimulusoffset and IOs with different terminations). Based on these simulations, you will generate reports with tables andwaveforms (2D plots, eye diagrams). You will then analyze these waveforms andtables with key signal quality and timing parameters to evaluate the power and signalintegrity performance of the DDR3-PAPBS. Next, you will replace the S-Parametersmodel of the parallel bus interface by its broadband circuit model or a newS-parameters model of different bandwidth, run simulations, generate reportsand analyze waveforms and tables to evaluate the power and signal integrityperformance of the DDR3-PAPBS. You will also model, simulate and analyze the DDR3-PAPBSby assigning a new S-Parameters model of the parallel bus interface generated withconnection ports to connect two memory components to the PCB block. Finally,you will simulate DDR4-PAPBS with ideal/non-ideal power, with/without on-dieparasitics, package parasitics etc., generate simulations based results andanalyze tables and waveforms (2D plots, eye diagrams, BER eye, Bathtub plots,impulse response etc.) to evaluate its power integrity and signal integrityperformance for each of the simulations.
