Real Modeling with Verilog-AMS

Length : 2 days

Course Description

In this advanced Engineer Explorer course, you learn how real number modeling using Verilog-AMS (wreal) enables high-performance digital-centric, mixed-signal verification. You must have a working knowledge of the Virtuoso^® AMS Designer simulator or you must take the Virtuoso AMS Designer course.

In this Engineer Explorer course, you learn how to model analog block operation as discrete real data for high-performance digital-centric, mixed-signal SoC verification. You explore the advanced capabilities of wreal by examining how wreal connections are resolved in mixed designs. You create Verilog-AMS wreal models and verify their functionality and performance, using the AMS Designer Incisive^® platform on the command-line and the AMS Designer Virtuoso design environment.

You examine how to create models using the Schematic Model Generator (SMG) and validate models using the AMS Design and Model Validation (amsDmv). You apply the Universal Verification Methodology-Mixed Signal (UVM-MS) for verification of analog and mixed-signal designs.

Learning Objectives

After completing this course, you will be able to:

• Identify how real number modeling using Verilog-AMS (wreal) enables high-performance digital-centric mixed-signal verification
• Create Verilog-AMS wreal models
• Verify the functionality and performance of the wreal models that you create using the Virtuoso AMS Designer simulator
• Use the advanced wreal modeling features
• Identify how wreal connections are resolved in mixed designs
• Apply the wreal modeling techniques for creating models
• Apply the Universal Verification Methodology-Mixed Signal (UVM-MS) to analog and mixed-signal designs
• Review some of the tips and tricks that you can apply while creating and simulating wreal models
• Create Verilog-AMS and wreal models using the Schematic Model Generator (SMG) and validate models using AMS Design and Model Validation (amsDmv)

Software Used in This Course

• Virtuoso AMS Designer Simulator
• Incisive Enterprise Simulator
• Digital Mixed-Signal Option to the Incisive Enterprise Simulator
• Virtuoso Analog Design Environment L
• Virtuoso Schematic Editor
• Virtuoso Visualization and Analysis XL
• SimVision Waveform Display
• Virtuoso Behavioral Modeling Option
• Virtuoso SMG run time

Software Release(s)

Incisive 14.1, IC 6.1.6ISR7

Modules in this Course

• Introduction to Real Modeling
• wreal Model Creation and Simulation
• wreal Modeling Techniques 
• Special Features of wreal
• Debugging Tips and Tricks
• Mixed-Signal Verification Capabilities
• Optional Appendixes
  • wreal Modeling Constructs and Guidelines
  • Schematic Model Generator (SMG)
  • AMS Design and Model Validation (amsDmv)
  • Licensing & Helpful irun Options
  • Waveform Viewers

Audience

• Analog/mixed-signal IC designers
• Analog/mixed-signal IC verification engineers
• Digital modeling and verification engineers

Prerequisites

You must have completed the following courses:

• Mixed Signal Simulations Using AMS Designer

• Behavioral Modeling with Verilog-AMSVerilog Language and Application

  Related Courses

  • Mixed Signal Simulations Using AMS Designer
  • Behavioral Modeling with Verilog-AMS
  • Verilog Language and Application
  • Analog Modeling with Verilog-A

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