SystemVerilog Advanced Register Verification Using UVM Training

Length: 2.5 Days (20 hours)

Become Cadence Certified

Course Description

This is an Engineer Explorer series course in which you explore advanced topics.

Universal Verification Methodology (UVM) register layer classes provide the basic building blocks for creating register reference models and protocol independent stimulus. The UVM register layer is tailored to allow engineers to quickly develop abstract, reusable, and scalable register-related verification environments.

In this course, you generate a configurable, reusable model to capture register functionality and functional coverage. You integrate the model into an existing UVM verification environment using protocol adapters. You explore different prediction modes to keep the model up-to-date with the Design Under Test (DUT). You create sequences using the powerful UVM register API for register and memory configuration, randomization, verification and self-checking. You connect the register model to scoreboard components. You explore techniques for modeling customized and unique register behavior. Finally, we cover advanced topics such as Active Monitoring and User-defined Frontdoors.

Learning Objectives

After completing this course, you will be able to:

• Use the features and capabilities of the UVM register layer
• Create configurable and reusable reference models for register behavior
• Integrate the register model into your verification environments using appropriate prediction
• Create self-checking sequences to verify register and memory behavior
• Enable, instantiate and control functional coverage in the register model
• Create and customize adapters to convery between register methods and UVC transactions
• Apply advanced modelling techniques to define unique register behavior
• Create advanced active monitors and user-defined frontdoors

Software Used in This Course

• Xcelium

Software Release(s)

XCELIUM2103

Modules in this Course

• Introduction to register modeling, register sequences, and the UVM register layer
• Generating a register model from an IP-XACT2014 XML description
• Integrating the register model into an existing verification environment
• Running built-in register sequences and tests
• Using register access methods to create protocol-independent register verification sequences
• Enhancing register sequences using introspection methods
• Exploring different prediction modes for keeping the register model and DUT in synchronization
• Customizing an adapter to interface with a UVM Verification Component (UVC)
• Enabling, instantiating and controlling functional coverage in the register model
• Updating a scoreboard to use a register model
• Techniques for defining customized register behavior
• Active monitoring to automatically update a register model when a DUT variable changes.
• A user-defined frontdoor to map a register method call to multiple UVC transactions.
• UVM and Cadence built-in register sequences and tests.
• Key updates in IP-XACT2014

Audience

• Design engineers
• Verification engineers

Prerequisites

You must have:

• A good working knowledge of UVM and SystemVerilog

Or you must have completed the following course:

• SystemVerilog Accelerated Verification with UVM

Related Courses

• SystemVerilog for Design and Verification
• SystemVerilog Accelerated Verification with UVM

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