Length: 2 days (16 Hours)
This is an Engineer Explorer series course in which you explore advanced topics.
Universal Verification Methodology (UVM) register layer classes provide the basic building blocks for creating register reference models and protocol independent stimulus. The UVM register layer is tailored to allow engineers to quickly develop abstract, reusable, and scalable register-related verification environments.
In this course, you generate a configurable, reusable model to capture register functionality and functional coverage. You integrate the model into an existing UVM verification environment using protocol adapters. You explore different prediction modes to keep the model up-to-date with the Design under Test (DUT). You create sequences using the powerful UVM register API for register and memory configuration, randomization, verification and self-checking. You connect the register model to scoreboard components. Finally you explore techniques for modeling customized and unique register behavior.
After completing this course, you will be able to:
- Use the features and capabilities of the UVM register layer
- Create configurable and reusable reference models for register behavior
- Integrate the register model into your verification environments using appropriate prediction
- Create self-checking sequences to verify register and memory behavior
- Apply advanced modeling techniques to define unique register behavior
Software Used in This Course
Modules in this Course
- Introduction to register modeling, register sequences, and the UVM register layer
- Generating a register model from an IP-XACT XML description.
- Creating an adapter to interface with a protocol-specific UVM Verification Component (UVC)
- Integrating the register model into an existing verification environment.
- Running built-in register sequences and tests
- Exploring different prediction modes for keeping the register model and DUT in synchronization
- Using the register access API to create protocol-independent register verification sequences
- Enhancing register sequences using introspection and advanced API methods
- Enabling functional coverage in the register model
- Techniques for defining customized register behavior
- Updating a scoreboard to use a register model
- Design engineers
- Verification engineers
You must have:
- A good working knowledge of UVM and SystemVerilog
Or you must have completed the following course:
- SystemVerilog Advanced Verification Using UVM