Length: 5 days (40 Hours)
Digital Badge Available
Course Description
In this course, you create an e language reusable block-level verification environment and simulate it with the Xcelium™ simulator and analyze the simulation with the SimVision™ graphical simulation analysis environment.
The course provides an introduction to the e language in the context of the Coverage-Driven Verification (CDV) methodology. You use the standard Universal Verification Methodology (UVM-e) to build a reusable verification environment.
Learning Objectives
After completing this course, you will be able to:
- Explain the need for and nature of the coverage-driven verification methodology
- Implement basic e syntax
- Generate constrained random values
- Define conditional struct subtypes
- Connect to and interact with the DUT
- Check the DUT behavior
- Cover the DUT functionality
- Develop an interface UVC for the Simple Packet Protocol
- Develop a sequence library for stimulus generation
- Develop a module UVC for the SPP router module
- Implement a mechanism to handle reset during verification
- Implement a mechanism to cleanly terminate the simulation
Software Used in This Course
- Xcelium Single-Core
- Integrated Metrics Center
Software Release(s)
XCELIUM2003, VMANAGER2003
Modules in this Course
- Introduction to Coverage-Driven Verification
- Write Simple e Programs
- Generating Constrained Random Values
- Creating Test Variations with AOP
- Connecting to and Interacting with the DUT
- Checking DUT Behavior
- Covering DUT Functionality
- Developing an Interface UVC
- Developing Sequences
- Developing a Module UVC
- Handling Reset and End-Of-Test
Audience
- Verification personnel wanting to use the e Functional Verification language and potentially also the e Universal Verification Methodology (e-UVM).
Prerequisites
You must have experience with or knowledge of the following:
- Any object-oriented language, such as C++, C#, SystemVerilog class constructs, Java or Python
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“The training has helped me to get a better understanding on how to make the verification environment more structured. The pace was good. All the labs were effective.”
Sindhu Joseph, Intel
“The course was very good! Awesome instructor. He is very friendly and competent in this topic.”
Rafet Ogul Tuerkel, Robert Bosch
“I am completely satisfied with the training. I learned a lot. I can feel an instant improvement. The training material was well organized and topics presented are of great usage.(...) I feel I enormously improved my knowledge. Thank you for this nice training!”
Marko Ilic, Infineon Technologies
“The Cadence Specman training is a great way of learning the e language, the Specman tool, and the Universal Verification Methodology (UVM).(...) I highly recommend this Cadence training.”
Raimund Soenning, Fujitsu
“This is the best online course I have attended so far.”
Robert Szczygiel, AGH University of Science and Technology
“I liked the in-depth knowledge of the instructor on specman/e and his passion/motivation on sharing this knowledge.”
Artemios Diakogiannis, Bosch Sensortec
"I really enjoyed the course and learned a lot. I especially liked the labs. With the labs it is much easier to understand everything that was covered in the lectures."
Francisco Torres, Broadcom
"My impression of the Specman training(...)is that it was extremely well done and it should help me in developing some reasonable knowledge of that language. It has also been very useful to follow the online training before the training in the class."
Dario Cardini, Robert Bosch
“(...)organized in a structured way taking us from the basics to writing an e-testbench. Presentation was very crisp and concise (...)enabled to grasp the concept quickly. Module labs and practice-exercises were very helpful (...)"
Deepthi Nanduri, University of Bristol