Allegro Package Designer

Length : 4 days

Course Description

In this course, you use the Allegro^® Package Designer system for the design and specification of manufacturing single-chip modules for single-, double-, or multilayered analog and digital packages. You develop a process flow, create cross section and design constraints, construct single-chip module connectivity, and route a design. You also create bond pads, make blind and buried padstacks, and output manufacturing data.

Learning Objectives

After completing this course, you will be able to:

• Develop a process flow to suit your design needs
• Create a new BGA package design and define the BGA pads and substrate cross section
• Add a standard die to the package design
• Define netlist connectivity for package and die pins
• Use the Constraint Manager to define physical, spacing, and electrical constraints
• Generate power rings and bond fingers, wire bond the design, and use the 3D viewer
• Define blind and buried vias, route signals interactively and automatically, and add voltage planes
• Output manufacturing data in Gerber or GDSII format, as well as create manufacturing documentation
• Create a new flip-chip package design

Software Used in This Course

• Allegro Package Designer L
• Cadence 3D Design Viewer
• Advanced Package Router Option

Software Release(s)

SPB172

Modules in this Course

• Introducing the Allegro Package Designer
• Starting a New Package Design
• Modifying the Netlist and Components
• Setting Design Rules
• Wire Bonding
• Routing
• Generating Manufacturing Output
• Creating a Flip-Chip Design

Audience

• This course is intended for package designers and design engineers

Prerequisites

You must have some experience with or knowledge of the following:

• Single or multichip design and construction

Related Courses

• SiP Layout

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