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Allegro Package Designer
Date | Version | Country | Location | |
---|---|---|---|---|
02 - 05 Aug 2022 | 17.2-2016 | Sweden | Kista-Stockholm Sweden |
ENROLL |
02 - 05 Aug 2022 | 17.2-2016 | United Kingdom Of Great Britain And Northern Ireland | Bracknell-London United Kingdom Of Great Britain And Northern Ireland |
ENROLL |
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
Version | Region | |
---|---|---|
17.2-2016 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length: 4 days (32 Hours)
Course Description
In this course, you use the Allegro® Package Designer system for the design and specification of manufacturing single-chip modules for single-, double-, or multilayered analog and digital packages. You develop a process flow, create cross section and design constraints, construct single-chip module connectivity, and route a design. You also create bond pads, make blind and buried padstacks, and output manufacturing data.
Learning Objectives
After completing this course, you will be able to:
- Develop a process flow to suit your design needs
- Create a new BGA package design and define the BGA pads and substrate cross section
- Add a standard die to the package design
- Define netlist connectivity for package and die pins
- Use the Constraint Manager to define physical, spacing, and electrical constraints
- Generate power rings and bond fingers, wire bond the design, and use the 3D viewer
- Define blind and buried vias, route signals interactively and automatically, and add voltage planes
- Output manufacturing data in Gerber or GDSII format, as well as create manufacturing documentation
- Create a new flip-chip package design
Software Used in This Course
- Allegro Package Designer L
- Cadence 3D Design Viewer
- Advanced Package Router Option
Software Release(s)
SPB172
Modules in this Course
- Introducing the Allegro Package Designer
- Starting a New Package Design
- Modifying the Netlist and Components
- Setting Design Rules
- Wire Bonding
- Routing
- Generating Manufacturing Output
- Creating a Flip-Chip Design
Audience
This course is intended for package designers and design engineers
Prerequisites
You must have some experience with or knowledge of the following:
- Single or multichip design and construction
Related Courses
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here

"The course was really good and I would highly recommend it to everyone."
Sandor Molnar, Cambridge Silicon Radio

”Instructor was great! Very pleasant personality, good knowledge of the subject, and a great pace and format to cover the material.”
Maryam Shahbazi, Lattice SemiConductor

"The instructor's knowledge of APD was very good and he was very good at answering our questions."
Andy Berry, Cambridge Silicon Radio