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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Integrity 3D-IC Platform
          • Cadence Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Voltus IC Power Integrity Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
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          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • 112G/56G SerDes
          • Chiplet and D2D
          • Denali Memory Interface and Storage IP
          • Interface IP
          • PCIe and CXL
          • Tensilica Processor IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
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      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • Allegro X Design Platform
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
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        • Photonics
        • RF / Microwave
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        • Automotive
        • Hyperscale Computing
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  • Physical Verification System



Physical Verification System

Online Courses
Instructor-Led Schedule
Date Version Country Location
Scheduled upon demandOn demand EXPRESS INTERESTINQUIRE
Version Region
21.1 Online ENROLL
20.1 Online ENROLL
Other Versions Online EXPRESS INTERESTINQUIRE

Length: 2 days (16 Hours)

Digital Badge Available

Course Description

Click here for a Course Preview. For faster and better performance in advanced node complex designs verification, Cadence recommends our latest tool, PegasusVerification System, instead of PVS. In this course, which has been designed for user-level physical design verification, you run DRC, LVS, ERC, PERC, FastXOR, and Constraint Validation checks to find and debug errors that are located in your design. You set up options, run DRC, and use PVS DRC Results Viewer or DRC DE to locate and fix design rule violations. You set up, run and debug ERC violations including stamping conflicts. You set up options, run LVS, and use the LVS debug environment to locate and repair errors like shorts and opens. You also run the Interactive Shorts Locator (ISL) to identify shorting locations. You will set up constraints using the Virtuoso® Constraint Manager and validate them with the PVS Constraint Validator. You then set up and run VIPVS (Virtuoso Integrated PVS) in Post-Edit and Verify-Design modes for in-design instant DRC checking, and use FastXOR to compare a stream file with an existing OpenAccess cellview.  In this course, the Virtuoso Layout Suite is used. The Physical Verification System (PVS) is integrated into the Virtuoso menus for easy access.  The "Extended Practice" module of this course has a free-form lab exercise, which is to be done using the skills that you learned in the previous modules. You have a physical layout with multiple errors and you have minimal instructions. You find and fix the errors, so that you have clean DRC and LVS runs.
NOTE: This course is compatible with IC 6.1.8 and ICADVM 201.1

Learning Objectives

After completing this course, you will be able to:

  • Check where PVS fits in the Cadence SSV Solution
  • Overview of the features and capabilities in PVS
  • Explore the Advanced Debug solutions in PVS
  • Set up and run PVS DRC in GUI and batch modes
  • Debug violations with the PVS Results Viewer, DRC DE, and Annotation Browser
  • Explore the PVS Configurator feature
  • Examine the PVS DRC Waivers flow
  • Explore the PVS Design Review platform
  • Set up and run PVS ERC in GUI and batch modes
  • Define and debug Stamping Conflicts 
  • Set up and run PVS PERC in GUI and batch modes
  • Explore topology checks from PVS PERC
  • Set up and run PVS LVS in GUI and batch modes
  • Clean shorts with the Interactive Shorts Locator
  • Troubleshoot LVS violations with the Graphical LVS Debugger
  • Set up and run VIPVS in Post-Edit and Verify Design modes
  • Create and manage snapshots for VIPVS
  • Run VIPVS in Dynamic Rules Filtering mode
  • Understand the concept of Constraint Validation in PVS
  • Invoke, set up, and run PVS CV in the Virtuoso platform
  • Debug Constraint Violations with PVS RV and Annotation Browser
  • Run PVS CV and debug violations in the Virtuoso Constraint Manager
  • Explore the various type of constraints supported by PVS CV
  • Set up and run PVS FastXOR in GUI and batch modes
  • Review PVS tips

Software Used in This Course

  • Virtuoso Layout Suite
  • Physical Verification System

Software Release(s)

PVS 21.1, IC 6.1.8, ICADVM 20.1

Modules in this Course

  • PVS Introduction
  • Design Rule Checking
  • Electrical Rules Checking
  • Programmable ERC (Optional)
  • Layout Versus Schematic
  • Virtuoso Interactive PVS
  • Constraint Validation in PVS
  • Running FastXOR (Optional)
  • Extended Practice for DRC and LVS (Optional)

Audience

  • Physical layout designers who need to verify layout designs

Prerequisites

You must have:

  • Knowledge and experience with physical design and verification
  • Familiarity with the Virtuoso Layout Suite

Related Courses

  • Pegasus Verification System
  • Physical Verification Language Rules Writer
  • Virtuoso Schematic Editor
  • Virtuoso Layout Design Basics
  • Assura Physical Verification
  • Virtuoso Layout Pro: T6 Constraint-Driven Flow and Power Routing
  • Virtuoso Connectivity-Driven Layout Transition

Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.

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“A well structured course with very patient instructor. Indeed will be taking home a lot of inputs from this 2 day course to help me and my colleague's future work at our organization. Looking at my fellow participants at the course, it feels like 'Yes we are in the game'..”

Thanuchith Vakkaliga-Raju, IMMS

“The course was efficient and very helpful for our Designers. For sure it will contribute to our productivity improvement.”

Mounir Jouini, EMMicroelectronic

"I found the videos very useful!"

Galante Sempere, Universidad de Las Palmas de Gran Canaria

 
 
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