Length : 3 days
There is increasing pressure on Hardware Designers to become bi-lingual. Design reuse, commercial Intellectual Property and distributed design teams are creating language neutral design methodologies, where an engineer may use VHDL for writing testbenches; Verilog and VHDL for RTL design and Verilog for gate level simulation.
VHDL for Verilog is an intensive course in VHDL for engineers who already have experience of Verilog. Based on Esperan's high-quality VHDL language and application training and delivered by trainers especially chosen for their in-depth knowledge of both languages, this course is the fastest and most effective method for Verilog engineers to understand the intricacies of VHDL and become proficient in the language.
- To provide a complete understanding of the essential concepts of VHDL and how these differ from Verilog.
- To give you practical experience of writing VHDL for synthesis and verification.
- To give you the knowledge to approach your VHDL or dual language design project with confidence.
This course is designed for developers who create designs for analog or digital ICs such as:
- IC Designers
- Analog/Mixed-Signal IC Designers
- Digital IC Designers
- ASIC Designers
- Design Engineers
- Chip Designers
- Layout Designers
This course assumes prior knowledge of Verilog, for example from attendance at Verilog Language and Application.
- VHDL language introduction
- Entity; architecture; hierarchy; configurations; processes; types; packages; libraries; comments; compilation order; language rules.
- Signals and Data-types
- Types; signal assignments; arrays; records; logic value sets.
- VHDL Operators
- Logical and relational operators; concatenation; array slices.
- Sequential Statements
- Process; if and case syntax; for loops; Multiple concurrent & sequential assignment statements; conditional and selected signal assignment.
- Sequential Statements and the Simulation Cycle
- Simulation cycle; wait statement; variables; loops
- Arithmetic Operators
- Operators; vendor arithmetic packages
- Definition of RTL Code
- Rules for describing combinational and registered logic in VHDL
- Synthesis Coding Styles
- State machine descriptions; if and case synthesis; initialization
- Advanced Synthesis Coding Styles
- Synthesis of variables; state vector encoding; synthesis directives; tri-states
- Functions & Procedures
- Function declaration and call; procedure declaration and call; parameter classes and modes; type qualification; resolution functions
- Advanced Concurrent VHDL
- Generics; generates
- Advanced Data Types
- Multi-dimensional arrays; type conversion and closely related types; subtypes; aliases
- Testbench Coding Styles
- Simple stimulus; assertions; clocks and resets; textio; pseudo-code based example
The labs have been designed to follow on from each other over the course of the training, building on code developed in each lab to create an overall design project.
The lab sessions include
- Familiarization with simulation and synthesis tools
- Describing and verifying combinatorial logic
- Creating registered logic
- Using vector arithmetic packages
- Structural design and hierarchy
- Verification using visualization of results
- State machine design
- Verification using script driven, self-checking testbenches
- Integration and verification of a third-party IP model