Length: 2 days (16 Hours)
This course teaches the IEEE SystemC TLM 2.0 library. The TLM 2.0 library provides model interoperability for memory-mapped SoC platforms. The library addresses the use cases of software application development and hardware/software integration, software performance analysis, hardware architecture analysis, and hardware functional verification. The library simultaneously meets the corresponding requirements for interoperability, relatively accurate timing, high simulation performance, and controllability and observability for debugging efforts.
After completing this course, you will be able to:
- Briefly describe the general purpose of TLM and the specific features of IEEE SystemC TLM 2.0, and map your objectives to the loosely-timed or approximately-timed modeling style
- Model a simple loosely-timed virtual platform, using the blocking transport interface, generic payload, convenience sockets, and temporally-decoupled processes
- Model a simple approximately-timed virtual platform, using the non-blocking transport interface, generic payload and extensions, base protocol and extensions, and convenience sockets, and adapt between the blocking and non-blocking transport interfaces
- Debug your virtual platform, using the direct memory interface, debug transport interface, and analysis interface, FIFO, and ports
Software Used in This Course
- Incisive® Enterprise Simulator - XL
Modules in this Course
- TLM Introduction
- Modeling a Loosely-Timed Virtual Platform
- Modeling an Approximately-Timed Virtual Platform
- Debugging Your Virtual Platform
- Hardware, software or system engineers who intend to develop or use virtual system platforms based upon the IEEE SystemC TLM 2.0 library.
You must have experience with or knowledge of the following:
- Fundamental design and/or verification practices.
- A practical working knowledge of IEEE Std. 1666™-2011 SystemC language fundamentals.
- C++ Language Fundamentals for Design and Verification
- SystemC Language Fundamentals
- Incisive SystemC, VHDL, and Verilog Simulation
- SystemC Synthesis with Stratus HLS