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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Integrity 3D-IC Platform
          • Cadence Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Voltus IC Power Integrity Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • 112G/56G SerDes
          • Chiplet and D2D
          • Denali Memory Interface and Storage IP
          • Interface IP
          • PCIe and CXL
          • Tensilica Processor IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • Allegro X Design Platform
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
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        • Hyperscale Computing
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  • SystemC Transaction-Level Modeling (TLM 2.0)



SystemC Transaction-Level Modeling (TLM 2.0)

Online Courses
Instructor-Led Schedule
Date Version Country Location
Scheduled upon demandOn demand EXPRESS INTERESTINQUIRE
Version Region
12.2 Online ENROLL
Other Versions Online EXPRESS INTERESTINQUIRE

Length: 2 days (16 Hours)

Course Description

This course teaches the IEEE SystemC TLM 2.0 library. The TLM 2.0 library provides model interoperability for memory-mapped SoC platforms. The library addresses the use cases of software application development and hardware/software integration, software performance analysis, hardware architecture analysis, and hardware functional verification. The library simultaneously meets the corresponding requirements for interoperability, relatively accurate timing, high simulation performance, and controllability and observability for debugging efforts.

Learning Objectives

After completing this course, you will be able to:

  • Briefly describe the general purpose of TLM and the specific features of IEEE SystemC TLM 2.0, and map your objectives to the loosely-timed or approximately-timed modeling style
  • Model a simple loosely-timed virtual platform, using the blocking transport interface, generic payload, convenience sockets, and temporally-decoupled processes
  • Model a simple approximately-timed virtual platform, using the non-blocking transport interface, generic payload and extensions, base protocol and extensions, and convenience sockets, and adapt between the blocking and non-blocking transport interfaces
  • Debug your virtual platform, using the direct memory interface, debug transport interface, and analysis interface, FIFO, and ports

Software Used in This Course

  • Incisive® Enterprise Simulator - XL

Software Release(s)

INCISIV122

Modules in this Course

  • TLM Introduction
  • Modeling a Loosely-Timed Virtual Platform
  • Modeling an Approximately-Timed Virtual Platform
  • Debugging Your Virtual Platform

Audience

  • Hardware, software or system engineers who intend to develop or use virtual system platforms based upon the IEEE SystemC TLM 2.0 library.

Prerequisites

You must have experience with or knowledge of the following:

  • Fundamental design and/or verification practices.
  • A practical working knowledge of IEEE Std. 1666™-2011 SystemC language fundamentals.

Related Courses

  • C++ Language Fundamentals for Design and Verification
  • SystemC Language Fundamentals
  • Incisive SystemC, VHDL, and Verilog Simulation
  • SystemC Synthesis with Stratus HLS

Click here to view course learning maps, and here for complete course catalogs.

Course ID: 84488

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