Length : 2 days
Course Description
In this course you will begin with an overview of parasitic extraction. The main function of this course is to allow you to use existing RCX or QX technology files to create a technology file for the new QRC extractor. You will use a compatibility flow which uses RCGeN or CAPGEN technology data files to illustrate the ability to run using the previous technology files. You will use the previous files to create one unified technology file which is the new comprehensive techfile. You will run transistor and cell level flows to illustrate the versatility of the QRC system of extraction. You will use the unified techfile flow running the Techgen command to integrate the new technology information. You will use options for the techgen command to illustrate many of the modes of techfile creation followed by running QRC extraction to prove the options.
You will learn the sections of the new ascii ictfile format used for simulation and compiling the new qrcTechFile. The information is very detailed for each of the sections including details of their available options.
Learning Objectives
Provide an overview of the QRC technology methodology.
- Use the existing RCGEN and QX files for the Techgen command
- Use options to configure the extraction modes you require.
- Set up options for multiplt corner extraction
- Set up options for sensitivity for techgen and extraction
- Verify options by running extraction and viewing extracted output.
Software
Assura Graphical User Interface Option
Assura Layout Vs. Schematic Verifier
Cadence QRC Extraction L
Virtuoso Layout Editor
Virtuoso Layout Suite L
Course Agenda
- QRC Technology Overview
- Technology File Setup
- Design Device Handling, Controlling Device Parasitics & Netlisting Output using Teechgen Options
- Multiple Process Corners and its Extraction in QRC
- Sensitivity Techfile Generation and Extraction in QRC
Audience
- CAD Developers
- Cadence Application Engineers
Prerequisites
You must have experience with or already have knowledge of the following:
- Cadence Physical Design Tools
- Cell Design
- CMOS devices
You must have experience with the following software:
- Assura Layout Vs. Schematic Verifier
- Virtuoso Layout Suite L
Special Notes
The course does use IC5141 and Assura317 for some of the labs. The rest of the labs use IC613 and Assura32. The Extraction uses EXT812.
Related Courses
- Cadence QRC User Cell-level Extraction
- Cadence QRC User Transistor-level Extraction
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Course ID: 84487
