Cadence QRC Techgen Developer

Learning Objectives

Provide an overview of the QRC technology methodology.

• Use the existing RCGEN and QX files for the Techgen command
• Use options to configure the extraction modes you require.
• Set up options for multiplt corner extraction
• Set up options for sensitivity for techgen and extraction
• Verify options by running extraction and viewing extracted output.

Software

Assura Graphical User Interface Option

Assura Layout Vs. Schematic Verifier

Cadence QRC Extraction L

Virtuoso Layout Editor

Virtuoso Layout Suite L

Course Agenda

• QRC Technology Overview
• Technology File Setup
• Design Device Handling, Controlling Device Parasitics & Netlisting Output using Teechgen Options
• Multiple Process Corners and its Extraction in QRC
• Sensitivity Techfile Generation and Extraction in QRC

Audience

• CAD Developers
• Cadence Application Engineers

Prerequisites

You must have experience with or already have knowledge of the following:

• Cadence Physical Design Tools
• Cell Design
• CMOS devices

You must have experience with the following software:

• Assura Layout Vs. Schematic Verifier
• Virtuoso Layout Suite L

Special Notes

The course does use IC5141 and Assura317 for some of the labs. The rest of the labs use IC613 and Assura32. The Extraction uses EXT812.

Related Courses

• Cadence QRC User Cell-level Extraction
• Cadence QRC User Transistor-level Extraction

Click here to view course learning maps, and here for complete course catalogs.