Behavioral Modeling with Verilog-AMS

Length : 2 days

Course Description

In this advanced Engineer Explorer course, you explore an in-depth approach to behavioral modeling of analog and mixed-signal design blocks and systems.

In this two-day course, you first examine digital modeling concepts and later analog and mixed-signal modeling concepts. You create parameterized Verilog-AMS models for analog and mixed-signal blocks and verify their functionality and performance using the Spectre^® AMS Designer simulator in the Virtuoso^® environment or the Xcelium™ Mixed-Signal Simulator environment.

As optional modules, you identify the key benefits and support of the Schematic Model Generator (SMG) for AMS languages such as Verilog-AMS and wreal models and the Waveform Specification (wave) feature in the ADE Assembler Environment for validating models.

Learning Objectives

After completing this course, you will be able to:

• Apply the concepts of behavioral modeling and know when to employ models to your advantage
• Create Verilog, Verilog-A, and Verilog-AMS behavioral models to perform given functions
• Verify the functionality and performance of the models that you create using the Virtuoso AMS Designer simulator
• Generate a library of common functions for smoothing discontinuous behavior and model common analog effects
• Explore some of the best practices for modeling analog components
• Interpolate with table models and explore the different system tasks and functions in Verilog-AMS

Software Used in This Course

• Spectre AMS Designer
• Spectre Simulators (MMSIM)
• Xcelium™ Single Core
• Virtuoso ADE Explorer/Assembler
• Virtuoso Visualization and Analysis XL
• SimVision™ Waveform Display

Software Release(s)

XCELIUM 17.10, IC 6.1.7 ISR16, SPECTRE17.1 (ISR2)

Modules in this Course

• Getting Started with AMS Modeling
• Refresher in Behavioral Verilog
• Verilog-AMS language constructs
• Continuity issues in modeling
• Modeling common analog effects: limiting, wave-shaping, and impedances
• Best practices for analog modeling
• Verilog-AMS mixed-signal operation
• Simulator functions in Verilog-AMS
• General modeling procedures

• Handling analog interdependencies
• Modeling in the frequency domain
• Schematic Model Generator (SMG)
• AMSD licensing and IRUN options
• Verilog-A usage and language summary
• Verilog-HDL usage and language summary
• Waveform viewers
• Waveform Specification in ADE Assembles

Audience

• Analog/Mixed-Signal IC Designers
• Analog/Mixed-Signal Verification Engineers
• CAD Engineers
• Library Developers

Prerequisites

You must have experience with the following software:

• AMS Designer Simulator
• Virtuoso ADE Explorer

Or you must have completed the following courses:

• Analog Modeling with Verilog-A
• Mixed-Signal Simulations Using AMS Designer

Related Courses

• Analog Modeling with Verilog-A
• Mixed-Signal Simulations Using AMS Designer
• Behavioral Modeling with VHDL-AMS

Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.