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      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
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          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Virtuoso RF Solution
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • System Design and Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation
          • Formal and Static Verification
          • FPGA-Based Prototyping
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Z1 Enterprise Emulation Platform
          • Protium X1 Enterprise Prototyping Platform
          • System VIP
          • RESOURCES
          • Flows
      • IP
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          • Denali Memory IP
          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
          • Verification IP
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          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
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          • RF / Microwave Design
          • Thermal Solutions
        • FEATURED PRODUCTS
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          • Celsius Thermal Solver
          • Sigrity Advanced SI
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  • Behavioral Modeling with Verilog-AMS



Behavioral Modeling with Verilog-AMS

Online Courses
Instructor-Led Schedule
Date Version Country Location
07 - 09 Jun 2021 17.10 Germany EMEA-Blended-Germany
Germany
ENROLL
Scheduled upon demandOn demand EXPRESS INTERESTINQUIRE
Version Region
14.2 Online ENROLL
Other Versions Online EXPRESS INTERESTINQUIRE

Length : 2 days

Course Description

In this advanced Engineer Explorer course, you explore an in-depth approach to behavioral modeling of analog and mixed-signal design blocks and systems.

In this two-day course, you first examine digital modeling concepts and later analog and mixed-signal modeling concepts. You create parameterized Verilog-AMS models for analog and mixed-signal blocks and verify their functionality and performance using the Spectre® AMS Designer simulator in the Virtuoso® environment or the Xcelium™ Mixed-Signal Simulator environment.

As optional modules, you identify the key benefits and support of the Schematic Model Generator (SMG) for AMS languages such as Verilog-AMS and wreal models and the Waveform Specification (wave) feature in the ADE Assembler Environment for validating models.

Learning Objectives

After completing this course, you will be able to:

  • Apply the concepts of behavioral modeling and know when to employ models to your advantage
  • Create Verilog, Verilog-A, and Verilog-AMS behavioral models to perform given functions
  • Verify the functionality and performance of the models that you create using the Virtuoso AMS Designer simulator
  • Generate a library of common functions for smoothing discontinuous behavior and model common analog effects
  • Explore some of the best practices for modeling analog components
  • Interpolate with table models and explore the different system tasks and functions in Verilog-AMS

Software Used in This Course

  • Spectre AMS Designer
  • Spectre Simulators (MMSIM)
  • Xcelium™ Single Core
  • Virtuoso ADE Explorer/Assembler
  • Virtuoso Visualization and Analysis XL
  • SimVision™ Waveform Display
This course uses Xcelium 17.10 with IC 6.1.7 ISR16 and SPECTRE17.1 software.
Both the command-line control-based model with the XRUN executable (AXUM), and the Virtuoso-based flow (AVUM) that uses Text Editors for coding and performs simulation using Spectre AMSD in the ADE Explorer are covered in the lab exercises.

Software Release(s)

XCELIUM 17.10, IC 6.1.7 ISR16, SPECTRE17.1 (ISR2)

Modules in this Course

  • Getting Started with AMS Modeling
  • Refresher in Behavioral Verilog
  • Verilog-AMS language constructs
  • Continuity issues in modeling
  • Modeling common analog effects: limiting, wave-shaping, and impedances
  • Best practices for analog modeling
  • Verilog-AMS mixed-signal operation
  • Simulator functions in Verilog-AMS
  • General modeling procedures
(Optional Appendixes)
  • Handling analog interdependencies
  • Modeling in the frequency domain
  • Schematic Model Generator (SMG)
  • AMSD licensing and IRUN options
  • Verilog-A usage and language summary
  • Verilog-HDL usage and language summary
  • Waveform viewers
  • Waveform Specification in ADE Assembles

Audience

  • Analog/Mixed-Signal IC Designers
  • Analog/Mixed-Signal Verification Engineers
  • CAD Engineers
  • Library Developers

Prerequisites

You must have experience with the following software:

  • AMS Designer Simulator
  • Virtuoso ADE Explorer

Or you must have completed the following courses:

  • Analog Modeling with Verilog-A
  • Mixed-Signal Simulations Using AMS Designer

Related Courses

  • Analog Modeling with Verilog-A
  • Mixed-Signal Simulations Using AMS Designer
  • Behavioral Modeling with VHDL-AMS

Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.

Course ID: 84455

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"Perfect."

Marian Poncik, ON Semiconductor

"Good overview course. Labs are very effectively supporting the learning progress.”

Andreas Weitzer, NXP Semiconductors

"Interesting and useful training with strong relation to my current job."

Jan Chromcak, ON Semiconductor

"Very valuable course with a good blend of lecture and lab exercises. Good style of lab exercises: first time to solve alone, then together on screen. Good structure: starting with Verilog, then VerilogA and finally combining both."

Josef Zipper, NXP Semiconductors

“Content was specifically tuned to what we need – very good!”

Sven de Knibber, Melexis

"The training was well prepared and very informative."

Martin Kejhar, ON Semiconductor

“I like the clear and understandable form of course material. The lecturer was able to answer all additional questions during the course.”

Andrey Kazarinov, Melexis

"Thanks a lot for this(…)course! Great lecturer. It is very clear and interesting(...). The pace is high but comfortable. Course content is well structured, easy to navigate."-Online Course-

Andrii Buzuluk, Melexis

 
 

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