Basic Static Timing Analysis

Length : 1 day

Course Description

In this course, you learn the basic concepts of static timing analysis and apply them to constrain a design. You apply these concepts to set constraints, calculate slack values for different path types, identify timing problems, and analyze reports generated by static timing analysis tools.

Learning Objectives

After completing this course, you will be able to:

• Identify and apply timing arc information from a library, including unateness, delays, and slew
• Identify cell delays from a library and calculate output slew degradation
• Use wire-load information to calculate net delays
• Identify the properties of a clock, including period, edges, slew, and duty cycle
• Apply setup and hold checks to diagnose design violations
• Identify timing path types and calculate slack values
• Set design-level and environmental constraints
• Set timing constraints, including clocks and external delays
• Set path exceptions
• Analyze reports to identify timing problems

Software Used in This Course

• Tempus™ Timing Signoff Solution

Software Release(s)

SSV161

Modules in this Course

• Introduction to Static Timing Analysis
• Understanding Cell Delay
• Understanding Net Delay
• Understanding Clocks
• Timing Checks
• Understanding Timing Paths
• Setting Constraints Using SDC
• Setting Timing Constraints
• Setting Path Exceptions
• Analyzing Timing Reports

Audience

• Verification Engineers
• Place and Route Designers
• IC Designers
• Hardware Engineers
• Electrical Engineers
• Designers
• ASIC Designers
• Design Engineers
• Circuit Designers
• Chip Designers

Prerequisites

You must have experience with or knowledge of the following:

• HDL
• Logic Design
• Basics of ASIC design

Related Courses

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