Basic Static Timing Analysis

After completing this course, you will be able to:

• Identify and apply timing arc information from a library, including unateness, delays, and slew
• Identify cell delays from a library and calculate output slew degradation
• Use wire-load information to calculate net delays
• Identify the properties of a clock, including period, edges, slew, and duty cycle
• Apply setup and hold checks to diagnose design violations
• Identify timing path types and calculate slack values
• Set design-level and environmental constraints
• Set timing constraints, including clocks and external delays
• Set path exceptions
• Analyze reports to identify timing problems