Virtuoso Schematic Editor

Length: 2 days (16 Hours)

Digital Badge Available

Course Description

In the Virtuoso^® Schematic Editor course, you learn to create and edit schematics for use with the suite of Cadence^® simulation and layout tools. You access both the L and XL tool suite capabilities. You place instances, wire schematics, and use hierarchical design concepts for the multi-level schematics. You then use the Verilog In and SPICE In translators to generate netlists and symbols.

You also create the circuit netlist and run a simulation.

In the Schematics XL, you add design rules using the Constraint Editor and Circuit Prospector assistants. In addition, you create inherited connections and generate layout instances from the schematic.

Learning Objectives

After completing this course, you will be able to:

• Use the Virtuoso Schematic Editor L and XL to capture design schematics, and create associated symbols, using library components
• Work with Virtuoso tool assistants and corresponding workspaces to increase productivity
• Use bindkeys to increase your efficiency and automate repetitive tasks
• Edit component properties and configurations
• Create netlists and set up simulations
• Run Verilog In and SPICE In translators to generate netlists and schematic symbols
• Describe flat and hierarchical schematics
• Add design constraints to schematics that are in the layout design
• Establish inherited connections to allow for variables to establish design properties on hierarchical instances

Software Used in This Course

• Virtuoso Schematic Editor L
• Virtuoso ADE Explorer
• Virtuoso Schematic Editor XL
• Spectre^® Classic Simulator

Software Release(s)

IC618ISR25, ICADVM201ISR25, SPECTRE201

Modules in this Course

• Introduction to the Virtuoso Design Environment
• Capturing Schematics
• Generating Symbols
• Navigating the Design Hierarchy
• Advanced Schematic Capture 
• Creating Constraints in Schematic XL
• Working with Inherited Connections

The Appendix A section contains a discussion on the overview of Cadence software. The Appendix B section contains a discussion on exploring the design hierarchy.

Audience

• Analog/Mixed-Signal IC Designers
• Analog Designers
• Analog IC Designers
• Chip Designers
• Custom Circuit Designers
• Design Engineers
• IC Designers
• RF Designers

Prerequisites

This is a basic level course to start creating designs in the Virtuoso Design Environment. There are no prerequisites for this class.

Related Courses

• Virtuoso ADE Explorer and Assembler S1: ADE Explorer and Single Test Corner Analysis
• Spectre Simulator Fundamentals S1: Spectre Basics

Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.