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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Integrity 3D-IC Platform
          • Cadence Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Voltus IC Power Integrity Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • 112G/56G SerDes
          • Chiplet and D2D
          • Denali Memory Interface and Storage IP
          • Interface IP
          • PCIe and CXL
          • Tensilica Processor IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • Allegro X Design Platform
          • RESOURCES
          • What's New in Allegro
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      • Computational Fluid Dynamics
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        • Hyperscale Computing
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        • Hyperscale Computing
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  • Virtuoso Schematic Editor



Virtuoso Schematic Editor

Online Courses
Instructor-Led Schedule
Date Version Country Location
Scheduled upon demandOn demand EXPRESS INTERESTINQUIRE
Version Region
IC6.1.8ISR25 Online ENROLL
IC6.1.8ISR17 Online ENROLL
IC6.1.8 Online ENROLL
Other Versions Online EXPRESS INTERESTINQUIRE

Length: 2 days (16 Hours)

Digital Badge Available

Course Description

In the Virtuoso® Schematic Editor course, you learn to create and edit schematics for use with the suite of Cadence® simulation and layout tools. You access both the L and XL tool suite capabilities. You place instances, wire schematics, and use hierarchical design concepts for the multi-level schematics. You then use the Verilog In and SPICE In translators to generate netlists and symbols.

You also create the circuit netlist and run a simulation.

In the Schematics XL, you add design rules using the Constraint Editor and Circuit Prospector assistants. In addition, you create inherited connections and generate layout instances from the schematic.

Learning Objectives

After completing this course, you will be able to:

  • Use the Virtuoso Schematic Editor L and XL to capture design schematics, and create associated symbols, using library components
  • Work with Virtuoso tool assistants and corresponding workspaces to increase productivity
  • Use bindkeys to increase your efficiency and automate repetitive tasks
  • Edit component properties and configurations
  • Create netlists and set up simulations
  • Run Verilog In and SPICE In translators to generate netlists and schematic symbols
  • Describe flat and hierarchical schematics
  • Add design constraints to schematics that are in the layout design
  • Establish inherited connections to allow for variables to establish design properties on hierarchical instances

Software Used in This Course

  • Virtuoso Schematic Editor L
  • Virtuoso ADE Explorer
  • Virtuoso Schematic Editor XL
  • Spectre® Classic Simulator

Software Release(s)

IC618ISR25, ICADVM201ISR25, SPECTRE201

Modules in this Course

  • Introduction to the Virtuoso Design Environment
  • Capturing Schematics
  • Generating Symbols
  • Navigating the Design Hierarchy
  • Advanced Schematic Capture 
  • Creating Constraints in Schematic XL
  • Working with Inherited Connections

The Appendix A section contains a discussion on the overview of Cadence software. The Appendix B section contains a discussion on exploring the design hierarchy.

Audience

  • Analog/Mixed-Signal IC Designers
  • Analog Designers
  • Analog IC Designers
  • Chip Designers
  • Custom Circuit Designers
  • Design Engineers
  • IC Designers
  • RF Designers

Prerequisites

This is a basic level course to start creating designs in the Virtuoso Design Environment. There are no prerequisites for this class.

Related Courses

  • Virtuoso ADE Explorer and Assembler S1: ADE Explorer and Single Test Corner Analysis
  • Spectre Simulator Fundamentals S1: Spectre Basics

Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.

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Course ID: 84443

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“Efficient course for me to get started with the Virtuoso environment. I appreciated the small group and that I had enough time to do the labs.”

Stefan Ganserer, Intel

"Instructor was great. There were many questions from me as well as other attendees. This helped me and I am sure helped others too. The course is very good and well organized.”

Authi Narayanan, Boeing

"Nice overall impression. The training is clearly structured and presented. There was enough time to individually discuss problems."

Steffen Schumann, Infineon Technologies

"Very well structured course. The labs reinforced the learning."

Eoin Carey, Macom

"Very good training. The topics were hand-selected to meet exactly the need of NXP designers. Perfect!"

Robert Entner, NXP Semiconductors

“We had a very good trainer for the course. Every question was answered by him and he explained all topics very well. My overall impression is that Cadence provides very good courses.”

Andrea Stueckler-Riavec, Intel

"I liked the quality of material that was taught, it helped me solve some of the problems I had using the software and work more efficiently.”

Odysseas Vamvakas, Aristotle University of Thessaloniki

"Very well prepared class. Very well prepared labs!"

Volker Pissors, Infineon Technologies

"Training is good and complements my knowledge!"-Online Course-

Ljubomir Djakovic, Elsys Eastern Europe

“I'm satisfied with the Virtuoso Schematic Editor course”-Online Course-

Kilian Roy, Dolphin Design

 
 

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