Length : 2 days
Digital Badge Available:
Course Description
In the Virtuoso® Schematic Editor course, you learn to create and edit schematics for use with the suite of Cadence® simulation and layout tools. You access both the L and XL tool suite capabilities. You place instances, wire schematics, use hierarchical design concepts for multi-level schematics. You then use the Verilog In and SPICE In translators to generate netlists and symbols.
You also create the circuit netlist and run a simulation.
In Schematics XL, you add design rules using the Constraint Editor and Circuit Prospector assistants. In addition, you create inherited connections and generate layout instances from the schematic.
Learning Objectives
After completing this course, you will be able to:
- Use Virtuoso Schematic Editor L and XL to capture design schematics, and create associated symbols, using library components
- Work with Virtuoso tool assistants and corresponding workspaces to increase productivity
- Use bindkeys to increase your efficiency and automate repetitive tasks
- Edit component properties and configurations
- Create netlists and set up simulations
- Run Verilog In and SPICE In translators to generate netlists and schematic symbols
- Describe flat and hierarchical schematics
- Add design constraints to schematics that are in the layout design
- Establish inherited connections to allow for variables to establish design properties on hierarchical instances
Software Used in This Course
- Virtuoso Schematic Editor L
- Virtuoso ADE Explorer
- Virtuoso Schematic Editor XL
- Spectre® Classic Simulator
Software Release(s)
IC 6.1.8 ISR5 and SPECTRE 18.1
Modules in this Course
- Introduction to the Virtuoso Design Environment
- Capturing Schematics
- Generating Symbols
- Navigating the Design Hierarchy
- Advanced Schematic Capture
- Creating Constraints in Schematic XL
- Working with Inherited Connections
The Appendix A section contains a discussion on Overview of Cadence Software. The Appendix B section contains a discussion on Exporting Design Hierarchy.
Audience
- Analog/Mixed-Signal IC Designers
- Analog Designers
- Analog IC Designers
- Chip Designers
- Custom Circuit Designers
- Design Engineers
- IC Designers
- RF Designers
Prerequisites
This is a basic level course to start creating designs in the Virtuoso Design Environment. There are no prerequisites for this class.
Related Courses
- Virtuoso ADE Explorer and Assembler S1: ADE Explorer and Single Test Corner Analysis
- Spectre Simulator Fundamentals S1: Spectre Basics
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
INSTRUCTIONAL VIDEOS
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SELF PACED ONLINE TRAINING
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“Efficient course for me to get started with the Virtuoso environment. I appreciated the small group and that I had enough time to do the labs.”
Stefan Ganserer, Intel
"Instructor was great. There were many questions from me as well as other attendees. This helped me and I am sure helped others too. The course is very good and well organized.”
Authi Narayanan, Boeing
"Nice overall impression. The training is clearly structured and presented. There was enough time to individually discuss problems."
Steffen Schumann, Infineon Technologies
"Very well structured course. The labs reinforced the learning."
Eoin Carey, Macom
"Very good training. The topics were hand-selected to meet exactly the need of NXP designers. Perfect!"
Robert Entner, NXP Semiconductors
“We had a very good trainer for the course. Every question was answered by him and he explained all topics very well. My overall impression is that Cadence provides very good courses.”
Andrea Stueckler-Riavec, Intel
"I liked the quality of material that was taught, it helped me solve some of the problems I had using the software and work more efficiently.”
Odysseas Vamvakas, Aristotle University of Thessaloniki
"Very well prepared class. Very well prepared labs!"
Volker Pissors, Infineon Technologies