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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Virtuoso RF Solution
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • System Design and Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation
          • Formal and Static Verification
          • FPGA-Based Prototyping
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Z1 Enterprise Emulation Platform
          • Protium X1 Enterprise Prototyping Platform
          • System VIP
          • RESOURCES
          • Flows
      • IP
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          • Interface IP
          • Denali Memory IP
          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
          • Verification IP
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
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        • PRODUCT CATEGORIES
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Sigrity Advanced SI
          • Sigrity Advanced PI
          • RESOURCES
          • System Analysis Resources Hub
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          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
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          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
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  • Virtuoso UltraSim Full-chip Simulator



Virtuoso UltraSim Full-chip Simulator

Instructor-Led Schedule
Date Version Country Location
Scheduled upon demandOn demand EXPRESS INTERESTINQUIRE

Length : 3 days

Course Description

In this course, you run FastSPICE simulation on large, complex, mixed-signal designs using the Virtuoso® UltraSim Full-chip Simulator. You explore the capabilities, methods, and modes of the simulator. You apply a variety of configurations that exploit the simulator's commands and options. You gain experience with hierarchical simulations, simulations of individual blocks, aged simulations, and EMIR analysis.

Learning Objectives

After completing this course, you will be able to:

  • Simulate complex mixed-signal circuits quickly, using the FastSPICE simulator and Virtuoso UltraSim Full-chip Simulator
  • Adjust the simulator's option settings to produce the proper tradeoff between accuracy and speed
  • Construct probes and measures for reporting circuit performance during simulation
  • Examine postprocessing measurement
  • Verify the circuit performance and identify the potential failure modes by running advanced analysis, including static and dynamic checks
  • Run hierarchical top-level simulations for prelayout, combining transistor-level schematics with structural Verilog HDL, behavioral Verilog-A models, or behavioral Verilog HDL models, digital stimulus (.vec, .vcd) files and postlayout simulation with adjustable parasitic reduction
  • Analyze the potential IR drop and electromigration (EM) problems in the layout by using Power IR/EM option and netlist-based EMIR
  • Effectively use the integration of FastSPICE simulation in the Analog Design Environment to improve silicon accuracy and time-to-market

Software Used in This Course

  • Virtuoso UltraSim Full-chip Simulator
  • SimVision Waveform Display
  • Virtuoso Analog Design Environment
  • Virtuoso Multimode Simulation
  • Cadence Design Framework II
  • Virtuoso Schematic Editor L
  • Virtuoso Visualization and Analysis XL

Software Release(s)

  • IC 6.1.6, MMSIM 12.1, Incisive 12.1

Course Agenda

Day 1

  • About This Course and Getting Help
  • Introduction to Virtuoso UltraSim FastSPICE Simulator
  • Virtuoso UltraSim Simulator Options
  • Probes and Measures

Day 2

  • Dynamic Checks UltraSim
  • Static Checks in UltraSim
  • Voltage Regulator and UltraSim Reliability Simulation

Day 3

  • Digital Stimulus Files
  • Postlayout Simulation in UltraSim
  • Electromigration and IR Drop in UltraSim
  • UltraSim Simulator in the Virtuoso Analog Design Environment

Audience

  • Analog and mixed-signal IC designers
  • Custom circuit designers
  • Analog IC designers
  • Analog designers

Prerequisites

You need a working knowledge of simulation techniques with netlist formats.

It is advantageous to take the following courses prior to taking this one:

  • Virtuoso Schematic Editor

  • Virtuoso Analog Design Environment

Related Courses

  • Virtuoso Analog Design Environment

Click here to view course learning maps, and here for complete course catalogs.

Course ID: 84438

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