Virtuoso UltraSim Full-chip Simulator

Length : 3 days

Course Description

In this course, you run FastSPICE simulation on large, complex, mixed-signal designs using the Virtuoso® UltraSim Full-chip Simulator. You explore the capabilities, methods, and modes of the simulator. You apply a variety of configurations that exploit the simulator's commands and options. You gain experience with hierarchical simulations, simulations of individual blocks, aged simulations, and EMIR analysis.

Learning Objectives

After completing this course, you will be able to:

• Simulate complex mixed-signal circuits quickly, using the FastSPICE simulator and Virtuoso UltraSim Full-chip Simulator
• Adjust the simulator's option settings to produce the proper tradeoff between accuracy and speed
• Construct probes and measures for reporting circuit performance during simulation
• Examine postprocessing measurement
• Verify the circuit performance and identify the potential failure modes by running advanced analysis, including static and dynamic checks
• Run hierarchical top-level simulations for prelayout, combining transistor-level schematics with structural Verilog HDL, behavioral Verilog-A models, or behavioral Verilog HDL models, digital stimulus (.vec, .vcd) files and postlayout simulation with adjustable parasitic reduction
• Analyze the potential IR drop and electromigration (EM) problems in the layout by using Power IR/EM option and netlist-based EMIR
• Effectively use the integration of FastSPICE simulation in the Analog Design Environment to improve silicon accuracy and time-to-market

Software Used in This Course

• Virtuoso UltraSim Full-chip Simulator
• SimVision Waveform Display
• Virtuoso Analog Design Environment
• Virtuoso Multimode Simulation
• Cadence Design Framework II
• Virtuoso Schematic Editor L
• Virtuoso Visualization and Analysis XL

Software Release(s)

• IC 6.1.6, MMSIM 12.1, Incisive 12.1

Course Agenda

Day 1

• About This Course and Getting Help
• Introduction to Virtuoso UltraSim FastSPICE Simulator
• Virtuoso UltraSim Simulator Options
• Probes and Measures

Day 2

• Dynamic Checks UltraSim
• Static Checks in UltraSim
• Voltage Regulator and UltraSim Reliability Simulation

Day 3

• Digital Stimulus Files
• Postlayout Simulation in UltraSim
• Electromigration and IR Drop in UltraSim
• UltraSim Simulator in the Virtuoso Analog Design Environment

Audience

• Analog and mixed-signal IC designers
• Custom circuit designers
• Analog IC designers
• Analog designers

Prerequisites

You need a working knowledge of simulation techniques with netlist formats.

It is advantageous to take the following courses prior to taking this one:

• Virtuoso Schematic Editor

• Virtuoso Analog Design Environment

Related Courses

• Virtuoso Analog Design Environment

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