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    • DESIGN EXCELLENCE
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        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
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          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
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          • Circuit Design
          • Circuit Simulation
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          • Layout Verification
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          • RESOURCES
          • Flows
      • System Design and Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation
          • Formal and Static Verification
          • FPGA-Based Prototyping
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
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          • Flows
      • IP
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          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
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          • Celsius Thermal Solver
          • Sigrity Advanced SI
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  • SKILL Development of Parameterized Cells



SKILL Development of Parameterized Cells

Online Courses
Instructor-Led Schedule
Date Version Country Location
01 - 02 Apr 2021 IC6.1.7 France EMEA-Blended-France
France
ENROLL
Scheduled upon demandOn demand EXPRESS INTERESTINQUIRE
Version Region
IC6.1.7 Online ENROLL
Other Versions Online EXPRESS INTERESTINQUIRE

Length : 2 days

Digital Badge Available

Course Description

This course describes the tools and methods of developing parameterized cells (PCells) in the SKILL® programming language, which is the Virtuoso® Design Environment extension language. A primary focus of the course is dedicated to an introduction and investigation of relative object design (ROD), a new technology providing powerful, flexible procedures for defining simple and complex layout objects and their relationships to each other.

Based upon a firm foundation in relative object design, PCell development will be explained in stages, beginning with creation of sizeable transistors and evolving into a fully parameterized inverter layout.

The SKILL and PCell IDE are introduced and used in the course to highlight the improvements to developing and debugging SKILL code and PCells.

How to design and test a Fluid PCell is covered and example code is provided. Adding CDF for PCell parameters and a discussion of the IC 6.1 connectivity model and example SKILL code is included.

This course places heavy emphasis on lab exercises.

Learning Objectives

After completing this course, you will be able to:

  • Understand how relative object design (ROD) SKILL functions can help you create layout objects and parameterized cells
  • Examine the architecture of ROD objects
  • Explore the versatility of ROD objects
  • Create and manipulate ROD objects interactively
  • Learn the concepts involved in developing PCells with SKILL
  • Define and use PCells using the PCell IDE
  • Make your PCells process-independent by applying technology file rules
  • Create a parameterized inverter layout
  • Create and test Fluid PCells
  • Add CDF entires for PCell parameters
  • Create PCells with auto-abutment for use in Virtuoso Layout Suite XL

Additional information in Appendices on:

  • SKILL IDE
  • Stretchable PCells

Software Used in This Course

 

  • Virtuoso Layout Suite L
  • Virtuoso Layout Suite XL
  • Cadence Design Framework II
  • SKILL Development Environment

 

Software Release(s)

IC 6.1.7

Modules in this Course

 

  • Introduction to Parameterized Cells
  • Using Relative Object Design (ROD) Commands to Create Design Data
  • Creating and Using SKILL Parameterized Cells
  • Enhanced Capabilities of SKILL Parameterized Cells

 

Audience

 

  • Library Developers
  • Layout Designers
  • Cadence SKILL Programmers
  • CAD Developers
  • This course is suitable for anyone interested in programmatic cell development.

 

Prerequisites

Hands-on experience with Cadence Design Framework II and the Virtuoso Layout Editor is required. You should be familiar with the SKILL Programming Language, comfortable with UNIX/Linux and have a good working knowledge of at least one text editor.

Related Courses

 

  • SKILL Language Programming Introduction
  • SKILL Language Programming
  • Advanced SKILL Language Programming
  • Virtuoso Layout Design Basics

Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.

Course ID: 84422

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“The content taught was absolutely the right choice - this will definitely improve my efficiency in writing PCells in the future. Great class! It absolutely met my expectations.”

Richard Geiger, Intel

“Very good and intense learning experience. In-depth lab material, giving a hands-on experience.”

Roshini Sachithanandan, Intel

“Everything looks very prepared and organized. The high percentage of labs through the course give me a feeling about the learned stuff. No improvement necessary from my point of view."

Thomas Zoeller, Anvo-Systems

 
 

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