Length : 2 days
Course Description
In this Assura® Verification course, you use the Assura Verification software to verify physical designs for Design Rule Checks (DRC), Electrical Rule Checks (ERC) and Layout-Versus-Schematic (LVS) checks. You could debug shorts in the design and locate them efficiently. In labs, you run DRC and LVS tools, and then you debug the error results.
Learning Objectives
After completing this course, you will be able to:
- Verify your physical IC design with Assura Verification
- Set up and run DRC, ERC and LVS
- Locate and display results from DRC and LVS runs
- Run verification in various input and run modes
Software Used in This Course
- Virtuoso Layout Suite L, Assura Verification
Software Release(s)
- IC 6.1.6, Assura Verification 4.1
Course Agenda
Day 1
- Introduction
- Using Assura Verification
- Operational details
- Inputs and outputs
- Interactive debugging environment
- DRC and LVS runs
- Running design-rule checks (DRC)
- DRC error debugging techniques
- Error layer window
- Setting up DRC run parameters
- Antenna check
- Density check
Day 2
- Running layout versus schematic (LVS) checks
- Understanding and debugging LVS check reports
- Setting up LVS run parameters
- Displaying errors using the graphical user interface
- Locating LVS errors
- Debugging LVS with multiple errors
- Using the main debugging tools
- Mismatched nets and mismatched devices
- Shorts locator and opens locator
- Malformed devices
- Pins, parameters, and rewire tools
- Unguided debugger lab module
- Running an electrical rules check (ERC)
- Appendix A & B (Optional)
Audience
- CAD Developers
Design Engineers
Layout Designers
Prerequisites
- Layout design experience
Physical verification experience
UNIX OS
Related Courses
Assura Rules Writer
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Course ID: 83029
