SystemVerilog Assertions Training

Length: 1.5 Days (12 hours)

Become Cadence Certified

Course Description

This course gives you an in-depth introduction to SystemVerilog Assertions (SVA), together with guidelines and methodologies to help you create, manage, and debug effective assertions for complex design properties. The course is packed with examples, case studies, and hands-on lab exercises to demonstrate real-life applications of SVA using both simulation and formal techniques. Different approaches to coding assertions and reuse issues are also examined.

Learning Objectives

After completing this course, you will be able to:

• State the motivation and methodology of using Assertion Based Verification (ABV)
• Define sequential and boolean properties and all of the different ways of aborting them
• List all the different ways of defining a property clock, including multi-clocked properties
• Demonstrate, with examples, good and bad SVA coding styles and show techniques for the most efficient creation of complex assertions
• Describe common behaviors which SVA cannot describe and how to overcome these issues
• List the issues regarding property set (verification) completeness
• Define liveness, fairness and safety properties that match your intent
• List the property forming SVA operators and constructs which are of practical use and those which are not, stating the reasons why
• List the property forming SVA operators and constructs which may not be efficient for formal analysis but may be useful in simulation
• Use the language features and methodologies for property reuse, including from formal to simulation and vice-versa
• State the motivation and methodology of defining coverage with SVA
• Correctly define Liveness, Fairness and Safety properties
• State the motivation and methodology of using Auxiliary (HDL helper) code

Software Used in This Course

• Jasper
• Xcelium
• Indago

Software Release(s)

JASPER2206 XCELIUM2203 INDAGO2203

Modules in this Course

Part 1 – Formal and Simulation Users (8 hours)

• Course Introduction
• Introduction to Assertion Based Verification (ABV)
• Simple Boolean Properties
• Sequences
• Coverage
• Liveness Properties
• Property Reuse
• Auxiliary Code Introduction
• Part 1 Conclusions and Next Steps

Part 2 – Simulation Users Only (4 hours)

• Sequence Operations
• Advanced SVA Topics
• Constructs Which Form Properties
  • Ones of pragmatic use
  • All of the others
• Verification Completeness
• Part 2 Conclusions and Next Steps

Audience

• Design and Verification Engineers
• Verification and Engineering Managers

Prerequisites

Before taking this course, you need to have already:

• One weeks experience in writing Verilog or SystemVerilog
• Attended a [System]Verilog training course, for example SystemVerilog for Design and Verification

All you need to know for now is how to:

• Write a boolean expression in [System]Verilog
• Describe a module
• Define an event control, for example @(posedge clk)

Related Courses

• Jasper Formal Fundamentals
• SystemVerilog for Design and Verification
• Xcelium Simulator
• Jasper Formal Expert

Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.