Length : 2 days
Digital Badge Available
Course Description
This course gives you an in-depth introduction to SystemVerilog Assertions (SVA), together with guidelines and methodologies to help you create, manage, and debug effective assertions for complex design properties. The course is packed with examples, case studies, and hands-on lab exercises to demonstrate real-life applications of SVA using both simulation and formal techniques. Different approaches to coding assertions and reuse issues are also examined
Learning Objectives
After completing this course, you will be able to:
- Explain the advantages of assertion-based verification (ABV) using SystemVerilog Assertions (SVA)
- Describe in detail the structure of SVA and demonstrate, with realistic examples, the full range of language features
- Demonstrate, with examples, good and bad SVA coding styles and show design techniques for the most efficient creation of complex assertions
- Describe, with case studies, a scalable methodology for reuse of SVA properties
- Describe common behaviors that SVA cannot describe and how to overcome these issues
- Explain the issues regarding verification completeness
- Explain what Formal Analysis is, what it does, how it works and run basic proofs
Software Used in This Course
- Xcelium™
- JasperGold®
Software Release(s)
- XLM201611, JASPER1612
Modules in this Course
Day 1
- Assertion-Based Verification (ABV)
- Assertion Basics
- Sequences
- Sequence Composition
- Advanced SVA Features
Day 2
- Coding Guidelines and Avoiding Common Problems
- Functional Coverage
- Formal Analysis Introduction
- Auxiliary Code
- Property Reuse
- Verification Components
- Property Set Completeness
Audience
- Design and Verification Engineers
Prerequisites
You must have experience with or knowledge of:
- An HDL Language: Either Verilog® or VHDL
Related Courses
JasperGold® Formal Fundamentals
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INSTRUCTIONAL VIDEOS
Training Bytes
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"I would personally prefer more blended training sessions in the future.(…) All instructions were clear and easy to follow. The greater lean towards self-study was very beneficial(…)."-Blended Training-
Mihai Chitic, Infineon Technologies
"I got an insight how valuable assertions can be. I will try to use more assertions to verify my design."
Andreas Szaj, NXP Semiconductors
"The course content and material was very well in line with expectations. I would like to highlight the competence and motivation of the trainer. (...)”
Joni Jantti, Ericsson
"Well-prepared and helpful course with excellent reference material."
Dmitry Shushunov, NXP Semiconductors
"The course was very relevant to current work. The content was very good and well instructed, and the lectures were very clear and well presented."
David Bean, Ericsson
"Very good training. I can now immediately use assertions in my designs."
Thomas Fina, NXP Semiconductors
"Good and helpful training to get an overview of SVA. Good lecture and labs.”
Bernd Rehberger, Freescale Semiconductor
"The training has delivered everything I expected. It gives all the necessary information to start using SVA in a real project."
Rabia Dogan, NXP Semiconductors
"The course(…)was very interesting and useful(…)I hope I can implement my new knowledge in my further work. Our trainer(…)was very good, explaining all issues and answering our questions accessibly."
Kirill Kapkaev, RC Module
"Very good course, well delivered."
Tim Joyce, ST Microelectronics
“I like the organization, contents and the teacher. It's always a pleasure to join the Cadence training, and this course was especially interesting for our team."
Pau Morant Sequi, Invensense