Conformal Low Power Verification with CPF Training

Length: 1 Day (8 hours)

Become Cadence Certified

Course Description

In this course, you learn to verify low-power designs using Conformal^® Low-Power Verification. In the labs, you debug practical examples of common power format (CPF) violations, functional and structural violations, and nonequivalences.

Learning Objectives

After completing this course, you will be able to:

• Identify features of the Conformal Low-Power software
• Identify the flows for low-power verification
• Identify power intent support in the Conformal Low-Power software
• Apply low-power checks on gate netlists with corresponding power intent
• Apply low-power checks on physical netlists with corresponding power intent
• Run low-power equivalency checks in different stages along with the supplied power intent

Software Used in This Course

• Conformal Low Power XL

Software Release(s)

CONFRML241

Modules in this Course

• Overview
• Preparation and Setup
• Power Intent Support
• Synthesis Verification
• Physical Verification
• Using Conformal Low-Power Effectively

Audience

• ASIC Designers
• Design Engineers
• Digital IC Designers
• FPGA Designers
• Hardware Engineers
• Logic Designers

Prerequisites

You must have experience with or knowledge of the following:

• Have a basic understanding of Verilog language and constructs
• Have a basic understanding of one of the three CPF power intent format
• Completed the Logic Equivalence Checking with Conformal course or
• Have equivalent experience with the Conformal Equivalence Checker tool

Or you must have completed the following courses:

• Conformal Equivalence Checking

Related Courses

Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.

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