Low-Power Simulation with CPF

Length: 2 days (16 Hours)

Course Description

This is an Engineer Explorer series course. The Engineer Explorer courses explore advanced topics.

This training provides an introduction to the concepts, challenges, and techniques for simulating and verifying low-power designs. It instructs how to communicate your design's low-power features to the simulator and downstream tools with the Common Power Format (CPF). It highlights the power-aware features of the Incisive® Enterprise family simulation and verification management tools.

Learning Objectives

After completing this course, you will be able to:

• Use digital simulation to verify power control design elements

Software Used in This Course

• EMG100 Incisive Enterprise Manager
• 29651 Incisive Enterprise Simulator - XL

Software Release(s)

• Incisive 13.1

Modules in this Online Course

• Course Introduction
• Introduction to Power-Aware Simulation
• Introduction to the Common Power Format
• Simulating a CPF-Based Power-Aware RTL Design
• Adding Power Modes to Your CPF-Based Power Simulation
• Instantiating Power-Aware Design IP
• Examining Power-Related Simulation Behavior
• Adding Power to Your Verification Plan
• Simulating a CPF-Based Power-Aware Gate-Level Design
• Conclusions and Next Steps

Audience

• Verification personnel using digital simulation to verify power-aware designs

Prerequisites

You must have experience with or knowledge of the following:

• Using the Incisive Enterprise Simulator to simulate and debug digital designs
• (Optional) Basics of low-power CMOS design

System Requirements for Online Courses

• For system requirements, click here.
• Cadence software, as listed above, installed and licensed

Related Courses

• Incisive SystemC, VHDL, and Verilog Simulation

• Low-Power Synthesis Flow with Encounter RTL Compiler

• Low-Power Implementation

• Conformal Low-Power Verification

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