Low-Power Simulation with CPF

Learning Objectives

After completing this course, you will be able to:

• Use digital simulation to verify power control design elements

Software Used in This Course

• EMG100 Incisive Enterprise Manager
• 29651 Incisive Enterprise Simulator - XL

Software Release(s)

• Incisive 13.1

Course Agenda

Note that this course can be tailored to better meet your needs – contact the Cadence training staff for specifics.

Day 1

• Course Introduction
• Introduction to Power-Aware Simulation
• Introduction to the Common Power Format
• Simulating a CPF-Based Power-Aware RTL Design
• Adding Power Modes to Your CPF-Based Power Simulation

Day 2

• Instantiating Power-Aware Design IP
• Examining Power-Related Simulation Behavior
• Adding Power to Your Verification Plan
• Simulating a CPF-Based Power-Aware Gate-Level Design
• Conclusions and Next Steps

Audience

• Verification personnel using digital simulation to verify power-aware designs

Prerequisites

You must have experience with or knowledge of the following:

• Using the Incisive Enterprise Simulator to simulate and debug digital designs
• (Optional) Basics of low-power CMOS design

Related Courses

• Incisive SystemC, VHDL, and Verilog Simulation

• Low-Power Synthesis with Encounter RTL Compiler

• Low-Power Implementation

• Low-Power Verification with Encounter Conformal

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