Tempus Signoff Timing Analysis and Closure Training

Length: 2 Days (16 hours)

Become Cadence Certified

Course Description

Note: This course is based on the default user interface and not the Stylus Common User Interface. 

We recommend you check with your design team or Cadence AE before selecting this course instead of the Tempus Signoff Timing Analysis and Closure with Stylus Common UI course. If there is not a clear preference, please select the Tempus Signoff Timing Analysis and Closure with Stylus Common UI course.

This course is a detailed exploration of the Tempus^™ Timing Signoff Solution, which supports distributed processing and enables fast static timing analysis with full signal integrity (SI) and glitch analysis, statistical variation (SOCV), and Multi-Mode and Multi-Corner (MMMC) analysis. In this course, you analyze a design for static timing and signal integrity issues, test parallel processing techniques, and run Tempus ECO to analyze the timing issues on large designs at the signoff stage and fix them using the Innovus™ Implementation System.

Learning Objectives

After completing this course, you will be able to:

• Identify timing analysis data requirements and import single corner designs, Multi-Mode Multi-Corner (MMMC) designs, and Multi-Supply Voltage (MSV) designs
• Identify and apply timing debug techniques using the Global Timing Debug interface
• Analyze a design for timing combined with signal integrity (SI)
• Run parallel processing techniques like distributed MMMC and Distributed Static Timing Analysis (DSTA)
• Run Tempus ECO analysis and timing closure flow between the Innovus Implementation and Tempus Signoff tools

Software Used in This Course

• Tempus Timing Signoff Solution
• Innovus Implementation System

Software Release(s)

SSV231, DDI231

Modules in this Course

• Introduction to the Tempus Timing Signoff Solution
• Design Import
• Timing Analysis and Reporting
• Timing Debug
• Crosstalk Analysis
• Parallel Processing
• Tempus ECO Flow

Audience

• Digital IC Designers
• IC Designers
• Place-and-Route Designers

Prerequisites

You must have experience with or knowledge of the following:

• Cadence physical design tools
• Static timing analysis

Related Courses

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