SystemVerilog for Design and Verification Training

Length: 5 Days (40 hours)

Become Cadence Certified

Course Description

This is an Engineer Explorer series course. The Engineer Explorer courses explore advanced topics.

This course gives you an in-depth introduction to the main SystemVerilog enhancements to the Verilog hardware description language (HDL), discusses the benefits of the new features, and demonstrates how design and verification can be more efficient and effective when using SystemVerilog constructs.

The course is broken down into two modules: The Design module examines improvements for RTL design and synthesis; the Verification module explores verification enhancements such as object-oriented design, assertions and randomization.

Learning Objectives

After completing this course you will be able to:

• Understand and use the SystemVerilog RTL design and synthesis features, including new data types, literals, procedural blocks, statements, and operators, relaxation of Verilog language rules, fixes for synthesis issues, enhancements to tasks and functions, new hierarchy and connectivity features, and interfaces.
• Appreciate and apply the SystemVerilog verification features, including classes, constrained random stimulus, coverage, strings, queues and dynamic arrays, and learn how to utilize these features for more effective and efficient verification.

Software Used in This Course

• XCELIUM
• VMGR (for IMC to view coverage)

Software Release(s)

XCELIUM2103, VMGR14

Modules in this Course

• SystemVerilog Overview
• Standard Data Types and Literals
• Procedures Statements and Procedural Blocks
• Operators
• User-Defined Data Types and Structures
• Hierarchy and Connectivity
• Static Arrays
• Tasks and Functions
• Interfaces
• Simple Verification Features
• Clocking Blocks
• Random Stimulus
• Basic Classes
• Polymorphism and Virtuality
• Class-Based Random Stimulus
• Interfaces in Verification
• Covergroup Coverage
• Queues and Dynamic and Associative Arrays (QDA)
• Introduction to Assertion-Based Verification (ABV)
• Introduction to SystemVerilog Assertions (SVA)
• Direct Programming Interface (DPI)
• Interprocess Synchronization

Audience

• Design engineers
• Verification engineers

Prerequisites

You must have:

• A working knowledge of Verilog
• The ability to navigate a file system and use a text editor
• A basic understanding of digital hardware design and verification

Related Courses

• Verilog Language and Application
• SystemVerilog Accelerated Verification with UVM1.2

Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.