Length : 2 days
Course Description
(Note: This course is based on the Stylus Common UI)
Virtuoso® Digital Implementation is a complete and automatic synthesis/place-and-route system. It enables capacity-limited block implementation for small digital components in the context of an advanced analog-driven mixed-signal design.
In this course, you learn the basics of synthesis and digital implementation by using the Virtuoso Digital Implementation software. You will explore synthesis, floorplanning, placement, power planning, clock-tree synthesis, timing optimization, and detail routing using VDI.
Learning Objectives
After completing this course, you will be able to:
- Run the recommended RTL synthesis flow
- Constrain designs and optimize for timing and power
- Floorplan the design
- Run placement, optimization and timing analysis
- Run clock-tree synthesis, detail routing and verification
- Run Stylus Flow Generation to automate the implementation flow
Software Used in This Course
Software Release(s)
GENUS181, INNOVUS181
Modules in this Course
- Refresh: Static Timing Analysis (STA) Fundamentals
- Virtuoso Digital Implementation Synthesis Fundamentals
- Synthesis Optimizations
- Power Optimization
- Test Synthesis
- Interfacing with Logic Equivalence Checking and Other Tools
- Virtuoso Digital Implementation Physical Implementation Overview
- Floorplanning the Design
- Planning and Routing Power
- Running Placement Optimization and Early Global Route
- Timing Analysis and Optimization
- Implementing the Clock Tree
- Detail Routing for Signal Integrity, Timing, and Design for Yield
- Design Finishing
- Summary of Implementation Steps
- Stylus Flow Generation
- Implementation Details
Audience
- Mixed-Signal Designers
- Custom IC Engineers
Prerequisites
You must have experience with or knowledge of the following:
- Place-and-Route Tools or Physical Design
Related Courses
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
