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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Virtuoso RF Solution
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • System Design and Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation
          • Formal and Static Verification
          • FPGA-Based Prototyping
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Z1 Enterprise Emulation Platform
          • Protium X1 Enterprise Prototyping Platform
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • Interface IP
          • Denali Memory IP
          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
          • Verification IP
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • System Analysis
        • PRODUCT CATEGORIES
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Sigrity Advanced SI
          • Sigrity Advanced PI
          • RESOURCES
          • System Analysis Resources Hub
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • What's New in Sigrity
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
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      • AI IP Portfolio
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  • Modus DFT Software Solution



Modus DFT Software Solution

Instructor-Led Schedule
Date Version Country Location
Scheduled upon demandOn demand EXPRESS INTERESTINQUIRE

Length : 1 day

Course Description

In this course, you will learn how to use of the Modus™ Test Solution Automatic Test Pattern Generation product for static pattern generation.

Learning Objectives

After completing this course, you will be able to:

  • Build a model (building the Modus Test Solution design database)
  • Build the fault model
  • Build test modes
  • Verify test structures (design rule checking)
  • Debug broken scan chains using the GUI and TCL command line techniques
  • Create static tests (ATPG)
  • Write vectors (Verilog, STIL, WGL)

Software Used in This Course

Modus Test Solution and Xcelium™ Parallel Simulator

Software Release(s)

MODUS172, XCELIUM1704

Modules in this Course

  • Modus Test Basics and Flow
  • How to Build a Model (Read the Netlist)
  • How to Build the Fault Model
  • How to Build Test Modes
  • How to Verify Test Structures
  • How to Debug Broken Scan Chains Using the Modus Test GUI
  • How to Debug Broken Scan Scans Using the TCL Command Line Interface (CUI)
  • How to Create Static Tests (ATPG)
  • How to Write Vectors (Verilog, STIL, WGL)

Audience

  • ASIC Designers
  • Chip Designers
  • Circuit Designers
  • Custom Circuit Designers
  • Design Engineers
  • Design for Testability Engineers
  • Digital IC Designers
  • IC Designers

Prerequisites

You must have experience with or knowledge of:

  • Test generation tools

Related Courses

  • Design for Test Fundamentals

Click here to view course learning maps, and here for complete course catalogs.

Course ID: 82137

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"Very good training. Very good tool.”

Andreas Schoch, Texas Instruments

“I successfully learned how to deploy Encounter Test for the various DFT-SCAN preparation checks and SCAN-chain insertion tasks. It was helpful to see during the training how to work with ET scripts in batch mode as well as how to deploy the GUI for resolving typical, basic DFT problems.(...)"

Christian Gehle, Texas Instruments

“Good course with an excellent presenter.”

Josy Bernard, Texas Instruments

“During the labs the trainer gave some additional hints which helped to work with the tool even better.”

Patrick Runkel, Texas Instruments

 
 

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