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        IP and SoC design verification

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        Computational fluid dynamics platform

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  • Specman Advanced Verification



Specman Advanced Verification Training

Instructor-Led Schedule
Date Version Country Location
Scheduled upon demandOn demand EXPRESS INTERESTINQUIRE

Length: 4 days (32 Hours)

Course Description

This is an Engineer Explorer course. You explore topics in a less formal and more user-directed pace. The course addresses advanced features of the e language and the Xcelium™ simulator implementation of the e language. To undertake this training, you must either have successfully completed the training course "Specman® for Block-Level Environment Developers" or have equivalent prior experience.

This course describes advanced features of the e language and Xcelium simulator implementation of the e language in the wider context of scaling and reusing verification environments from the block level through large system-level environments. You typically construct such environments from components of multiple languages, such as e, SystemC, and SystemVerilog. The course describes and follows the UVM recommendations including the Cadence UVM e extensions.

Cadence Design Systems arranges this training in response to user inquiries, holds the training at the user-selected site, and focusses on the user selection of topics.

The training can address a variety of advanced topics including:

  • Exploring best practices to support system debug
  • Linting your e code with the Xcelium HDL Analysis tool
  • Improving coverage metrics by using the coverage API, configurable ranges and coverage-driven distributions
  • Extending the e language by defining macros
  • Modeling registers and memories by using the open-source UVM package vr_ad
  • Dynamically accessing the e program structure and values by using the reflection API
  • Implementing multiple-driver and multiple-thread sequence use models
  • Improving sequence driving performance by using the sequence API
  • Implementing multi-language communication, synchronization and configuration by using the UVM Multi-language Open Architecture library
  • Improving regression performance by adopting efficient simulation use models and by using the Specman Advanced Option (SAO)

Learning Objectives

After completing this course, you will be able to:

  • Implement best practices to support design and testbench debug
  • Customize and utilize the Xcelium HDL Analysis to "lint" your testbench code
  • Improve coverage metrics by using the coverage API, configurable ranges and coverage-driven distributions
  • Extend the e language by defining macros
  • Model registers and memories by using the vr_ad package
  • Dynamically access the e program structure and values by using the reflection API
  • Implement multiple-driver and multiple-thread sequence use models
  • Improve sequence driving performance by using the sequence API
  • Implement multi-language communication, synchronization and configuration by using the UVM Multi-language Open Architecture library
  • Improve regression performance by adopting efficient simulation use models and by using the Specman Advanced Option (SAO)

Software Used in This Course

  • Xcelium Simulator

Software Release(s)

XCELIUM 20.03

Modules in this Course

  • Debug Patterns
  • Linting
  • Comprehensive Specman Coverage Implementation
  • Macros
  • Register and Memory Modelling
  • Reflection API in the e Language
  • Advanced Sequences
  • UVM-ML Open Architecture Library – Basics
  • Using the Specman Tool Efficiently

Audience

Current module-level UVM e testbench designers who want to:

  • Improve their testbench design productivity
  • Improve their testbench performance

Prerequisites

You must have either:

  • Successfully completed the training "Specman Fundamentals for Block-Level Environment Developers", or
  • Equivalent practical experience with the e language, UVM e compliant verification environments, and the Xcelium™ simulator implementation of the e language

Related Courses

  • Specman Fundamentals for Block-Level Environment Developers
  • Metric Driven Verification Using Cadence vManager

Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.

Course ID: 82133

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“I think everything was perfect.(...) great course with a lot of fruitful discussions. Trainer knowledge is to be highlighted”

Manuel Soto, Bosch Sensortec

“Comprehensive overview covering advanced options of Specman. Valuable feedback from experienced trainer and application engineer.”

Martin Höllerer, Heidenhain

"The advanced course touched some high end topics which contributed to my work. (...) These topics were not in my everyday use and I intend to use them more thoroughly. This course can contribute even to the expert user."

Yagel Mishni, Ceragon Networks

"An enjoyable training course!"

Gabriel Duffy, STMicroelectronics

"Worth going to. The teacher was very competent and capable to understand the questions and needs that sometimes have been asked in a very fuzzy way."

Michael Sommer, Infineon Technologies

"I liked the time that I spent in the course. It was useful although not all topics were new to me. The instructor was very nice, I liked his way of presenting."

Sandra Schuetz, Bosch Sensortec

"A lot of energy spent by the instructor to help us understanding the training. Always available and always ready to change the way to explain for our understanding."

Yanick Paviot, STMicroelectronics

"I had a very good experience in this course, it exceeded my expectations(...)enriching and interesting."

Noa Gurman, Nuvoton

“The instructor is highly competent. He can explain not only all the content in the slides but also the questions we raised during the lecture.”

Zhang Shihao, Bosch Sensortec

“interactive and customized training, overall satisfying”

Martin Höllerer, Heidenhain

 
 
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