Design for Test Fundamentals Training

Length: 1/2 Days (4 hours)

Become Cadence Certified

Course Description

This is a half-day introduction to the concepts and terminology of Automatic Test Pattern Generation (ATPG) and Digital IC Test.

Learning Objectives

After completing this course, you will be able to:

Understand and discuss why we test, what we test, and how we test, including:

• List out the reasons for testing and its different aspects
• Describe how to perform testing
• Compare defects and faults
• Identify commonly used fault models
• Demonstrate generation of test patterns for combinational, sequential, and scanned circuits
• Identify basic DFT design rules
• Illustrate special tests for memory, cores, self-test, compression, I/Os, and so on
• List out test escapes and their effect on test volume and product quality
• Identify the basic diagnostic capabilities

Software Used in This Course

None

Software Release(s)

None

Modules in this Course

The Basics:

• The Purpose of Testing
• The Target of Testing
• The Basics of Testing

Audience

• VHDL Designers
• Logic Designers
• Library Developers
• IC Designers
• Hardware Engineers
• Engineering Managers
• Electrical Engineers
• Digital IC Designers
• Designers
• Design for Testability Engineers
• Design Engineers
• Custom Circuit Designers
• Chip Designers
• Cadence Application Engineers
• ASIC Designers
• CAD System Administrators
• CAD Engineers

This class is open to anyone curious about the basics of testing digital ICs. Anyone involved in digital IC design or support can benefit from it.

Prerequisites

There are no prerequisites for taking this class.

Related Courses

• Test Synthesis with Genus Stylus Common UI 
• ATPG Flow with Modus DFT Software Solution

Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.