Length: 1 day (8 Hours)
In this course, you use the Incisive® mixed-language simulator to run event-driven digital simulation in one of three languages: SystemC, VHDL, or Verilog. While you learn the process of compilation, elaboration, simulation, and interactive debugging, you apply the most commonly used options in each of those processes. You apply solutions in SystemC, VHDL, and Verilog, choosing which language to use in the labs.
After completing this course, you will be able to:
- Compile, elaborate, link, and simulate a design using the Cadence Incisive Simulator IES tool.
- Debug a design with the interactive simulation interface.
- Examine many of the capabilities of the SimVision graphical simulation analysis environment and apply these capabilities in the context of a scripted debug scenario.
- Debug a design with the textual interactive simulation interface.
- Briefly examine most of the interactive commands to see what capabilities are available and how you can use them in a script to drive batch regression tests, and practice these capabilities in the context of a scripted debug scenario.
Software Used in This Course
Modules in this Course
- Incisive Simulation Introduction
- Using the irun Utility
- The Incisive Graphical Interface
- The Incisive Textual Interface
- Debugging with SimVision™ and Textual/Batch Commands
- Appendix: Introduction to Indago™ Debug Analyzer App
Hardware, software, or verification designers who are already familiar with SystemC, VHDL, and Verilog.
You must already have:
- Familiarity with the SystemC, VHDL, or Verilog languages
- Familiarity with hardware design, software design, and verification methodology
- Basic UNIX literacy, including the ability to navigate the file system and open, edit, move, and delete files.
- SystemC Language Fundamentals
- VHDL Application Workshop
- Verilog Language and Application
- Incisive Simulation of PSL Assertions
- Incisive Comprehensive Coverage