VHDL Language and Application Training

Length: 5 Days (40 hours)

Become Cadence Certified

Course Description

The VHDL Language and Application course offers a comprehensive exploration of VHDL and its application to ASIC and programmable logic design. It provides a solid background in the use and application of VHDL to digital hardware design. This training course covers all aspects of the language, from basic concepts and syntax through synthesis coding styles and guidelines to advanced language constructs and design verification. It also touches upon ASIC library design concepts.

Learning Objectives

The learning objectives of this course include:

• Using basic and advanced VHDL language details, and advanced application issues, including:
  • Synthesis coding styles to build sophisticated designs and testbenches
• Analyzing design organization and management
• Using real-world hardware-orientated examples
• Setting up and running simulation using the Xcelium simulator

Software Used in This Course

• Xcelium
• Genus Synthesis Solution

Software Release(s)

XCELIUM2209, GENUS201

Modules in this Course

Day 1

• Course Introduction
• Application Introduction
• Language Introduction
• Signals and Data Types
• VHDL Operators
• Sequential Statements

 Day 2

• Concurrent and Sequential Statements
• Simulation Cycle and Process Control
• Variables and Sequential Statements
• Arithmetic Operators
• VHDL Coding Styles

Day 3

• The Synthesis Process
• Definition of RTL Code
• Synthesis of Mathematical Operators
• FSM Design and Synthesis
• Synthesis Coding Styles

Day 4

• Functions and Procedures
• Advanced Concurrent VHDL
• Advanced Data Types
• Testbench Coding Styles
• Testbench Applications

Day 5

• Gate-Level Simulation
• Application of Configurations
• Design Organization and Management

Audience

• Design Engineers
• Verification Engineers

Prerequisites

You must have:

• Good working knowledge of any of the programming languages
• Knowledge of logic design
• Hands-on experience in coding

Related Courses

• SystemVerilog for Design and Verification
• Verilog Language and Application

Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.