VHDL Language and Application

Length: 5 days (40 Hours)

Course Description

This course offers a comprehensive exploration of the VHDL hardware description language and its application to digital hardware design and verification. The course covers all the fundamental aspects of VHDL from basic concepts and syntax, through synthesis coding styles and guidelines, to advanced language constructs and design verification.

Learning Objectives

After completing this course you will be able to:

• Understand and use the essential concepts and constructs of VHDL
• Create efficient, effective RTL code for synthesis according to industry-standard guidelines
• Verify VHDL designs using test environments of significant capability and complexity
• Write VHDL for synthesis and verification in a project-based environment using the latest tools

Software Used in This Course

• Encounter RTL Compiler L
• Incisive Enterprise Simulator L

Software Release(s)

• INCISIV111, RC91

Course Agenda

Days 1-2: Language Basics

• VHDL language introduction
• Design units and main language concepts
• Processes and sequential statements
• Simulation execution, sensitivity lists, and wait statements
• Variables and variable use
• Operators, operator overloading, and arithmetic packages
• Coding styles for testbenches, RTL, and behavioral code

Day 3: Synthesis Coding Styles

• RTL coding styles and guidelines for high-quality, reusable, synthesizable code
• Coding styles for efficient hardware synthesis
• Finite State Machines (FSMs) and state vector encoding
• Synthesis implications with variables, branching statements and other constructs

Days 4-5: Advanced Constructs and Verification

• Procedures and functions
• Generics, generates, and blocks
• Unconstrained, type-indexed, and multi-dimensional arrays
• Types, sub-types, closely-related types, and type conversions
• Coding styles and strategies for generating test stimulus
• Design organization and management
• Options and strategies for using configurations
• Modeling timing in VHDL
• Key updates in VHDL2001 and VHDL2008

Audience

• Design engineers
• Verification engineers

Prerequisites

You must have:

• The ability to navigate a file system and use a text editor
• A basic understanding of digital hardware design and verification
• Prior experience with a procedural programming language

Related Courses

• Incisive SystemC, VHDL, and Verilog Simulation

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