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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Integrity 3D-IC Platform
          • Cadence Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Voltus IC Power Integrity Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • 112G/56G SerDes
          • Chiplet and D2D
          • Denali Memory Interface and Storage IP
          • Interface IP
          • PCIe and CXL
          • Tensilica Processor IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • Allegro X Design Platform
          • RESOURCES
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  • Perl for EDA Engineering



Perl for EDA Engineering

Instructor-Led Schedule
Date Version Country Location
30 May - 01 Jun 2022 2.0 Israel EMEA-Blended-Israel
Israel
ENROLL
10 - 12 Oct 2022 2.0 France EMEA-Blended-France
France
ENROLL
05 - 07 Dec 2022 2.0 France EMEA-Blended-France
France
ENROLL
Scheduled upon demandOn demand EXPRESS INTERESTINQUIRE

Length: 3 days (24 Hours)

Course Description

This course provides a detailed introduction to the EDA applications of Perl, covering all of its core features, showing its application in analyzing large quantities of textual data and offering expert tips on how to construct effective scripts. Conventional Perl classes tend to concentrate on web programming applications. This class has been specifically written to emphasize the Perl features which are of more interest to EDA engineers and CAD departments.

About Perl for EDA

Perl is a general purpose scripting language with outstanding features for text, file and process manipulation. In the EDA world, these features make Perl extremely useful for applications such as:

  • Extracting specific data from a text file, e.g. tool reports, logs, code or netlists
  • Translating or tweaking code formats between tools
  • Generating code, e.g. testbenches, stimulus vectors, code wrappers or shells
  • Executing multi-tool operations in a design flow

Learning Objectives

In this course you will:

  • Gain an in-depth understanding of the essential concepts of Perl.
  • Understand the Perl syntax
  • Learn about the different variable types in Perl - scalars, arrays and hashes
  • Understand Flow Control
  • Understand the idea of context
  • Create complex data structures by means of references
  • Read and Write - explore Perl's IO system
  • Create reusable code by means of subroutines and modules
  • Master Regular Expressions in Perl
  • Use the Perl Debugger to trace problems

Prerequisites

Knowledge of at least one other programming or scripting language and some basic Unix experience are required. No prior knowledge of Perl is required.

Course Summary

Perl Fundamentals

Describing the basic syntax and concepts of Perl. Constructing robust, reusable Perl modules using best-practice guidelines for coding, documentation and testing.

Data Processing

Understanding how to create, read, update and delete common Perl data structures (arrays, hashes, arrays-of-arrays, arrays-of-hashes etc). Using Regular Expression syntax to extract and edit specific data from such structures and from text files. Manipulating files and directories in Perl.

Course Agenda

Day 1

  • Course Introduction
  • Getting Help
  • Executing Perl Programs
  • Syntax
  • Variables

Day 2

  • Pragmas and Modules
  • Flow Control
  • Subroutines
  • FILE I/O

Day 3

  • Regular Expressions
  • Modules
  • The Perl debugger
  • Perl and the File System

Lab sessions include:

  • Text search, substitution and processing
  • Creating and manipulating data structures
  • Use of subroutines
  • Module management and installation
  • Recursively programming

Click here to view course learning maps, and here for complete course catalogs.

Course ID: 82075

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“Thank you for the GREAT Training!  I appreciate it! The trainer has used both his experience and his excellent knowledge to answer all trainees questions! The labs (...) are tailored to enable trainees to master PERL!”-Blended Course-

Maidin Grahic, Infineon

"Excellent training session. The best Cadence training session I have received."

Paula Kelleher, NXP Semiconductors

"The course was clear and easy to follow. The main concepts have been well explained."

Nicolas Montigon, STMicroelectronics

 
 

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