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DESIGN EXCELLENCE

  • Digital Design and Signoff
  • Custom IC
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Digital Design and Signoff

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

PRODUCT CATEGORIES

  • Logic Equivalence Checking
  • SoC Implementation and Floorplanning
  • Functional ECO
  • Low-Power Validation
  • Synthesis
  • Power Analysis
  • Constraints and CDC Signoff
  • Silicon Signoff and Verification
  • Library Characterization
  • Test

FEATURED PRODUCTS

  • Integrity 3D-IC Platform
  • Cadence Cerebrus Intelligent Chip Explorer
  • Genus Synthesis Solution
  • Innovus Implementation System
  • Tempus Timing Signoff Solution
  • Voltus IC Power Integrity Solution
  • Pegasus Verification System
  • RESOURCES
  • Flows

Custom IC / Analog / RF Design

Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

PRODUCT CATEGORIES

  • Circuit Design
  • Circuit Simulation
  • Layout Design
  • Layout Verification
  • Library Characterization
  • RF / Microwave Solutions

FEATURED PRODUCTS

  • Spectre X Simulator
  • Spectre FX Simulator
  • Virtuoso Layout Suite
  • Virtuoso ADE Product Suite
  • Virtuoso Advanced Node
  • Voltus-Fi Custom Power Integrity Solution
  • RESOURCES
  • Flows

Verification

Offering a full verification flow to our customers and partners that delivers the highest verification throughput in the industry

PRODUCT CATEGORIES

  • Debug Analysis
  • Virtual Prototyping
  • Emulation and Prototyping
  • Static and Formal Verification
  • Planning and Management
  • Simulation
  • Software-Driven Verification
  • Verification IP
  • System-Level Verification IP

FEATURED PRODUCTS

  • vManager Verification Management
  • Jasper C Apps
  • Helium Virtual and Hybrid Studio
  • Xcelium Logic Simulation
  • Palladium Enterprise Emulation
  • Protium Enterprise Prototyping
  • System VIP
  • RESOURCES
  • Flows

IP

An open IP platform for you to customize your app-driven SoC design.

PRODUCT CATEGORIES

  • 112G/56G SerDes
  • Chiplet and D2D
  • Denali Memory Interface and Storage IP
  • Interface IP
  • PCIe and CXL
  • Tensilica Processor IP

RESOURCES

  • Discover PCIe

IC Package Design and Analysis

Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.

PRODUCT CATEGORIES

  • Cross-Platform Co-Design and Analysis
  • IC Package Design
  • SI/PI Analysis
  • SI/PI Analysis Point Tools
  • Flows

Multiphysics System Analysis

Cadence® system analysis solutions provide highly accurate electromagnetic extraction and simulation analysis to ensure your system works under wide-ranging operating conditions.

PRODUCT CATEGORIES

  • Computational Fluid Dynamics
  • Electromagnetic Solutions
  • RF / Microwave Design
  • Signal and Power Integrity
  • Thermal Solutions

FEATURED PRODUCTS

  • Clarity 3D Solver
  • Clarity 3D Solver Cloud
  • Clarity 3D Transient Solver
  • Celsius Thermal Solver
  • Fidelity CFD
  • Sigrity Advanced SI
  • Celsius Advanced PTI
  • RESOURCES
  • System Analysis Center
  • System Analysis Resources Hub
  • AWR Free Trial

Embedded Software

PCB Design and Analysis

Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

PRODUCT CATEGORIES

  • Design Authoring
  • PCB Layout
  • Library and Design Data Management
  • Analog/Mixed-Signal Simulation
  • SI/PI Analysis
  • SI/PI Analysis Point Tools
  • RF / Microwave Design
  • Augmented Reality Lab Tools

FEATURED PRODUCTS

  • Allegro Package Designer Plus
  • Allegro PCB Designer
  • Allegro X Design Platform
  • RESOURCES
  • What's New in Allegro
  • Advanced PCB Design & Analysis Resources Hub
  • Flows

Computational Fluid Dynamics

AI / Machine Learning

AI IP Portfolio

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  • Photonics
  • RF / Microwave
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Training

  • Custom IC / Analog / RF Design
  • Languages and Methodologies
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  • IC Package
  • PCB Design
  • System Design and Verification
  • Tensilica Processor IP
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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Integrity 3D-IC Platform
          • Cadence Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Voltus IC Power Integrity Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • 112G/56G SerDes
          • Chiplet and D2D
          • Denali Memory Interface and Storage IP
          • Interface IP
          • PCIe and CXL
          • Tensilica Processor IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • Allegro X Design Platform
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
      • Computational Fluid Dynamics
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
    • CADENCE CLOUD
    • VIEW ALL PRODUCTS
  • Solutions
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
  • Support
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        • Support Process
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        • Custom IC / Analog / RF Design
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        • IC Package
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        • System Design and Verification
        • Tensilica Processor IP
      • Support
        • Support Process
        • Online Support
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        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • Training
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
      • Support
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • Training
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
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  • Custom IC / Analog / RF Design (72)
  • Digital Design and Signoff (29)
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All Courses Learning Map

Cadence Training Services learning maps provide a comprehensive visual overview of the learning opportunities for Cadence customers. They provide recommended course flows as well as tool experience and knowledge levels to guide students through a complete learning plan. Learning Maps cover all Cadence Technologies and reference courses available worldwide.

  • Custom IC / Analog / RF Design
    Advanced Nodes (ICADV)
    • Virtuoso Layout for Advanced Nodes
    • Virtuoso Layout for Advanced Nodes and Methodology Platform
    • Virtuoso Layout for Advanced Nodes: T1 Place and Route
    • Virtuoso Layout for Advanced Nodes: T2 Electromigration
    Circuit Design and Simulation
    • Analog Modeling and Simulation with SPICE
    • Design Checks and Asserts
    • High-Performance Spectre Simulation
    • Mixed Signal Simulations Using Spectre AMS Designer
    • Simulation and Analysis Using OCEAN
    • Spectre Accelerated Parallel Simulator
    • Spectre Simulator Fundamentals S1: Spectre Basics
    • Spectre Simulator Fundamentals S2: Large-Signal Analyses
    • Spectre Simulator Fundamentals S3: Small-Signal Analyses
    • Spectre Simulator Fundamentals S4: Measurement Description Language
    • Spectre eXtensive Partitioning Simulator for Mixed-Signal Designs
    • Variation Analysis Using the Virtuoso Variation Option
    • Virtuoso ADE Explorer and Assembler S1: ADE Explorer and Single Test Corner Analysis
    • Virtuoso ADE Explorer and Assembler S2: ADE Assembler and Multi Test Corner Analysis
    • Virtuoso ADE Explorer and Assembler S3: Sweeping Variables and Simulating Corners
    • Virtuoso ADE Explorer and Assembler S4: Monte Carlo Analysis, Real-Time Tuning and Run Plans
    • Virtuoso ADE Verifier S1: Setup, Run and View Verification Results
    • Virtuoso ADE Verifier S2: Reference Flow and Analog Coverage Using the Setup Library Assistant
    • Virtuoso Analog Design Environment
    • Virtuoso Analog Simulation: T1 The Virtuoso Analog Design XL Environment
    • Virtuoso Analog Simulation: T2 Creating Sweeps and Running Corner Analysis
    • Virtuoso Analog Simulation: T3 Monte Carlo Simulations Using ADEXL
    • Virtuoso Analog Simulation: T4 Sensitivity Analysis and Circuit Optimization Using ADE(G)XL
    • Virtuoso Schematic Editor, Schematic, simulation, design entry, constraint editor, circuit prospector, hierarchy, instance, wiring, schematic capture, inherited connection, Verilog In, SPICE In, assistant, workspace
    • Virtuoso Spectre Pro S1: DC Algorithm
    • Virtuoso System Design Platform
    • Virtuoso Visualization and Analysis
    Circuit Modeling
    • Analog Modeling with Verilog-A
    • Behavioral Modeling with VHDL-AMS
    • Behavioral Modeling with Verilog-AMS
    • Real Modeling with SystemVerilog
    • Real Modeling with Verilog-AMS
    • SystemVerilog Real Number Modeling (SV-RNM) Based Advanced Verification
    Circuit Simulation
    • Command-Line Based Mixed-Signal Simulations with the Xcelium Use Model
    • Mixed Signal Simulations Using Spectre AMS Designer
    • Real Modeling with SystemVerilog
    • Simulation and Analysis Using OCEAN
    • Spectre Accelerated Parallel Simulator
    • Spectre Simulator Fundamentals S3: Small-Signal Analyses
    • Spectre Simulator Fundamentals S4: Measurement Description Language
    • Virtuoso Spectre Pro S2: AC, XF, STB, and Noise Analyses
    • Virtuoso Spectre Pro S3: Transient Algorithm
    • Virtuoso Spectre Pro S4: Measuring Accurate Fourier Transforms
    • Virtuoso Spectre Pro S5: Transient Noise
    • Virtuoso UltraSim Full-chip Simulator
    IC CAD
    • Advanced SKILL Language Programming
    • SKILL Development of Parameterized Cells
    • SKILL Language Programming
    • SKILL Language Programming Fundamentals
    • SKILL Language Programming Introduction
    Layout Verification
    • Pegasus Verification System
    • Physical Verification Language Rules Writer
    • Physical Verification System
    • Quantus Transistor-Level T1: Overview and Technology Setup
    • Quantus Transistor-Level T2: Parasitic Extraction
    • Quantus Transistor-Level T3: Extracted View Flows and Advanced Features
    Physical Design
    • Enhancing Layout Productivity with Virtuoso Layout Pro Training Webinar
    • Pegasus Verification System
    • Physical Verification System
    • Quantus Transistor-Level T1: Overview and Technology Setup
    • Quantus Transistor-Level T2: Parasitic Extraction
    • Quantus Transistor-Level T3: Extracted View Flows and Advanced Features
    • SKILL Language Programming Introduction
    • Virtuoso Abstract Generator
    • Virtuoso Connectivity-Driven Layout Transition
    • Virtuoso Floorplanner
    • Virtuoso Layout Design Basics
    • Virtuoso Layout Pro: T1 Environment and Basic Commands (L)
    • Virtuoso Layout Pro: T2 Create and Edit Commands (L)
    • Virtuoso Layout Pro: T3 Basic Commands (XL)
    • Virtuoso Layout Pro: T4 Advanced Commands (XL)
    • Virtuoso Layout Pro: T5 Interactive Routing (XL)
    • Virtuoso Layout Pro: T6 Constraint-Driven Flow and Power Routing
    • Virtuoso Layout Pro: T7 Module Generator and Floorplanner (XL/GXL)
    • Virtuoso Layout Pro: T8 Debugging Layout Issues
    • Virtuoso Layout Pro: T9 Virtuoso Design Planner
    • Virtuoso Layout for Advanced Nodes and Methodology Platform
    • Virtuoso Simulation Driven Routing (SDR)
    RF Design
    • 5G mmWave Handset System Design – S1: RFIC (Transceiver) Design
    • Spectre RF Analysis using Harmonic Balance
    • Spectre RF Analysis using Shooting Newton Method
  • Digital Design and Signoff
    Equivalence Checking
    • Conformal ECO
    • Conformal Equivalence Checking
    • Conformal Low Power Verification Using IEEE 1801
    • Conformal Low-Power Verification
    • Custom Equivalence Checking with Conformal EC
    Implementation
    • Innovus Block Implementation with Stylus Common UI
    • Innovus Clock Concurrent Optimization Technology for Clock Tree Synthesis
    • Innovus Clock Concurrent Optimization Technology with Stylus Common UI
    • Innovus Hierarchical Implementation with Stylus Common UI
    • Innovus Implementation System (Block)
    • Innovus Implementation System (Hierarchical)
    • Innovus Low-Power Flow with Stylus Common UI
    • Low-Power Flow with Innovus Implementation System
    • Virtuoso Digital Implementation
    Silicon Signoff
    • Basic Static Timing Analysis
    • Cadence RTL-to-GDSII Flow
    • Joules Power Calculator
    • Tempus Signoff Timing Analysis and Closure
    • Tempus Signoff Timing Analysis and Closure with Stylus Common UI
    • Voltus Power Grid Analysis and Signoff with Stylus Common UI
    • Voltus Power-Grid Analysis and Signoff
    Synthesis and Test
    • Advanced Synthesis with Genus Stylus Common UI
    • Design for Test Fundamentals
    • Fundamentals of IEEE 1801 Low-Power Specification Format
    • Genus Synthesis Solution
    • Genus Synthesis Solution with Stylus Common UI
    • Joules Power Calculator
    • Low-Power Synthesis Flow with Genus Stylus Common UI
    • Modus DFT Software Solution
    • Test Synthesis with Genus Stylus Common UI
  • IC Package
    Cross-Platform Co-Design and Analysis
    • OrbitIO System Planner
    • SiP Layout
    IC Package Design
    • Allegro Package Designer
    • Allegro Package Designer Plus
    • SiP Layout
    SI/PI Analysis
    • Allegro Sigrity PI
    • Allegro Sigrity Package Assessment and Model Extraction
    • Allegro Sigrity SI Foundations
    • Sigrity Aurora
    SI/PI Analysis Point Tools
    • Allegro Sigrity Package Assessment and Model Extraction
    • Model Generation and Analysis using PowerSI and Broadband SPICE
    • Sigrity PowerDC and OptimizePI
    • Sigrity PowerDC and OptimizePI (Français)
    • Sigrity SystemSI for Parallel Bus and Serial Link Analysis
    • TopXplorer SystemSI for Parallel Bus and Serial Link Analysis
  • Languages and Methodologies
    Assertions
    • SystemVerilog Assertions
    Behavioral Language for AMS Simulation
    • Behavioral Modeling with VHDL-AMS
    • Behavioral Modeling with Verilog-AMS
    • Real Modeling with SystemVerilog
    • Real Modeling with Verilog-AMS
    • SystemVerilog Real Number Modeling (SV-RNM) Based Advanced Verification
    High-Speed PCB Design
    • PCB Design at RF - Multi-Gigabit Transmission, EMI Control, and PCB Materials
    Scripting
    • Perl for EDA Engineering
    • Tcl Scripting for EDA + Intro to Tk
    Specman and UVMe
    • Specman Advanced Verification
    • Specman Fundamentals for Block-Level Environment Developers
    SystemC
    • C++ Language Fundamentals
    • SystemC Language Fundamentals
    • SystemC Synthesis with Stratus HLS
    • SystemC Transaction-Level Modeling (TLM 2.0)
    SystemVerilog and UVM
    • Essential SystemVerilog for UVM
    • SystemVerilog Accelerated Verification with UVM
    • SystemVerilog Advanced Register Verification Using UVM
    • SystemVerilog Assertions
    • SystemVerilog for Design and Verification
    • SystemVerilog for Verification
    Verilog and VHDL
    • VHDL Language and Application
    • Verilog Language and Application
  • PCB Design
    Analog/Mixed-Signal Simulation
    • Advanced PSpice for Power Users
    • Allegro AMS Simulator
    • Allegro AMS Simulator Advanced Analysis
    • Analog Simulation with PSpice
    • Analog Simulation with PSpice Advanced Analysis
    • Simulation Analogique-Mixte PSpice Avancée (Français)
    Design Authoring
    • Allegro Design Entry HDL Basics
    • Allegro Design Entry HDL Front-to-Back Flow
    • Allegro Design Entry HDL SKILL Programming Language
    • Allegro Design Entry Using OrCAD Capture
    • Allegro Design Reuse
    • Allegro EDM Design Entry HDL Front-to-Back Flow
    • Allegro FPGA System Planner
    • Allegro System Architect
    • Allegro System Capture
    • Allegro Team Design Authoring
    • OrCAD CIS
    • OrCAD Capture Constraint Manager PCB Flow
    Library and Design Data Management
    • Allegro Design Workbench for Librarians
    • Allegro EDM PCB Librarian
    • Allegro EDM for Administrators
    • Allegro EDM for Engineers and Designers
    • Allegro PCB Librarian
    PCB Layout
    • Advanced Design Verification with the RAVEL Programming Language
    • Allegro Design Entry Using OrCAD Capture
    • Allegro High-Speed Constraint Management
    • Allegro PCB Editor Advanced Methodologies
    • Allegro PCB Editor Basic Techniques
    • Allegro PCB Editor Intermediate Techniques
    • Allegro PCB Editor SKILL Programming Language
    • Allegro PCB Router Basics
    • Allegro RF PCB
    • Allegro Tool Setup and Configuration
    • Allegro Update Training
    SI/PI Analysis
    • Allegro Sigrity PI
    • Allegro Sigrity Package Assessment and Model Extraction
    • Allegro Sigrity SI Foundations
    • PCB Design at RF - Multi-Gigabit Transmission, EMI Control, and PCB Materials
    • Signal and Power Integrity Analysis with Sigrity Aurora Webinar
    SI/PI Analysis Point Tools
    • Celsius Thermal Solver
    • Clarity 3D Solver
    • Essential High-Speed PCB Design for Signal Integrity
    • Model Generation and Analysis using PowerSI and Broadband SPICE
    • Sigrity Aurora
    • Sigrity PowerDC and OptimizePI
    • Sigrity PowerDC and OptimizePI (Français)
    • Sigrity SystemSI for Parallel Bus and Serial Link Analysis
    • TopXplorer SystemSI for Parallel Bus and Serial Link Analysis
  • System Design and Verification
    Emulation and Acceleration
    • Protium Rapid Prototyping Platform
    Formal Verification
    • Embracing Datapath Verification with Jasper C2RTL App Webinar
    • JasperGold Formal Expert
    • JasperGold Formal Fundamentals
    • SVA, Formal and Jaspergold Fundamentals for Designers
    • SystemVerilog Assertions
    Planning and Management
    • Foundations of Metric Driven Verification
    • Metric Driven Verification Using Cadence vManager
    • vManager Tool Usage in Batch Mode
    Scripting
    • Perl for EDA Engineering
    • Tcl Scripting for EDA + Intro to Tk
    Simulation and Testbench and Debug
    • Incisive Functional Safety Simulator
    • Incisive SystemC, VHDL, and Verilog Simulation
    • Low-Power Simulation with CPF
    • Low-Power Simulation with IEEE Std 1801 UPF
    • Perspec System Verifier – Basic
    • Xcelium Fault Simulator
    • Xcelium Integrated Coverage
    • Xcelium Simulator
    Specman and UVMe
    • Specman Advanced Verification
    • Specman Fundamentals for Block-Level Environment Developers
    SystemC
    • C++ Language Fundamentals
    • SystemC Language Fundamentals
    • SystemC Synthesis with Stratus HLS
    • SystemC Transaction-Level Modeling (TLM 2.0)
    SystemVerilog and UVM
    • Essential SystemVerilog for UVM
    • SystemVerilog Accelerated Verification with UVM
    • SystemVerilog Advanced Register Verification Using UVM
    • SystemVerilog for Design and Verification
    Verification IP
    • VIP Basic Building Blocks and Usage
    Verilog and VHDL
    • VHDL Language and Application
    • Verilog Language and Application
  • Tensilica Processor IP
    ConnX Baseband DSP
    • Tensilica ConnX 110 and 120 DSP Family
    • Tensilica ConnX B10 DSP
    • Tensilica ConnX B20 DSP
    • Tensilica ConnX BBE16EP Baseband Engine
    • Tensilica ConnX BBE32EP Baseband Engine
    • Tensilica ConnX BBE64EP Baseband Engine
    FloatingPoint DSP
    • Tensilica FloatingPoint DSP Family
    Fusion DSP
    • Tensilica Fusion F1 DSP
    • Tensilica Fusion G3 DSP
    • Tensilica Fusion G6 DSP
    HiFi Audio DSP
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    • Tensilica Xtensa Neural Network Compiler v2

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