All Courses Learning Map
Cadence Training Services learning maps provide a comprehensive visual overview of the learning opportunities for Cadence customers. They provide recommended course flows as well as tool experience and knowledge levels to guide students through a complete learning plan. Learning Maps cover all Cadence Technologies and reference courses available worldwide.
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Computational Fluid Dynamics
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Custom IC / Analog / Microwave & RF Design
Circuit Design and Simulation- Analog Circuit Design and Simulation Onboarding
- Analog Modeling and Simulation with SPICE
- Analyzing Simulation Results Using Virtuoso Visualization and Analysis
- Custom Analog IP Migration in Virtuoso Studio
- Design Checks and Asserts in Spectre Simulator
- Electromagnetic Simulations Using the EMX Solver
- FastSpice Simulations Using Spectre FX Simulator
- High-Performance Spectre Simulation
- Reliability Analysis in Virtuoso Studio
- Spectre FMC in Virtuoso ADE
- Spectre Simulator Fundamentals S1: Spectre Basics
- Spectre Simulator Fundamentals S2: Large-Signal Analyses
- Spectre Simulator Fundamentals S3: Small-Signal Analyses
- Spectre Simulator Fundamentals S4: Measurement Description Language
- Using Spectre Effectively S1: Accelerating DC Analysis
- Using Spectre Effectively S2: Accelerating Transient Analysis
- Virtuoso ADE Explorer and Assembler S1: ADE Explorer and Single Test Corner Analysis
- Virtuoso ADE Explorer and Assembler S2: ADE Assembler and Multi Test Corner Analysis
- Virtuoso ADE Explorer and Assembler S3: Sweeping Variables and Simulating Corners
- Virtuoso ADE Explorer and Assembler S4: Monte Carlo Analysis, Real-Time Tuning and Run Plans
- Virtuoso ADE Verifier S1: Setup, Run and View Verification Results
- Virtuoso ADE Verifier S2: Reference Flow and Analog Coverage Using the Setup Library Assistant
- Virtuoso Heterogeneous Integration: EM Analysis of ICs Using the EMX Solver
- Virtuoso Schematic Editor
- Virtuoso Spectre Transient Noise
- Virtuoso System Design Platform
Microwave & RF Design- 5G mmWave Handset System Design – S1: Simulation and Verification of the RFIC (Transceiver)
- Microwave Office for RF Designers
- Planar EM Analysis in AWR Microwave Office
- Spectre RF Analyses S1: Large-Signal Analyses Using Harmonic Balance and Shooting Newton
- Spectre RF Analysis Using Shooting Newton Method
- Spectre RF Analysis using Harmonic Balance
Physical Design- Boost Your Layout Productivity with Virtuoso Studio
- Cadence Analog IC Design Flow
- Virtuoso Abstract Generator
- Virtuoso Connectivity-Driven Layout Transition
- Virtuoso Floorplanner
- Virtuoso Layout Design Basics
- Virtuoso Layout Pro: T1 Environment and Basic Commands
- Virtuoso Layout Pro: T2 Create and Edit Commands
- Virtuoso Layout Pro: T3 Basic Commands
- Virtuoso Layout Pro: T4 Advanced Commands
- Virtuoso Layout Pro: T5 Interactive Routing
- Virtuoso Layout Pro: T6 Constraint-Driven Flow and Power Routing
- Virtuoso Layout Pro: T7 Module Generator and Floorplanner
- Virtuoso Layout Pro: T8 Virtuoso Concurrent Layout Editing
- Virtuoso Layout Pro: T9 Virtuoso Design Planner
- Virtuoso Layout for Photonics Design - T1
- Virtuoso Studio Features
Physical Verification- Pegasus Verification System
- Physical Verification Language Rules Writer
- Physical Verification System
- Quantus Transistor-Level T1: Overview and Technology Setup
- Quantus Transistor-Level T2: Parasitic Extraction
- Quantus Transistor-Level T3: Extracted View Flows and Advanced Features
- Virtuoso Layout Design Basics
- Virtuoso Layout Pro: T4 Advanced Commands
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Digital Design and Signoff
Implementation- Artificial Intelligence and Machine Learning Fundamentals
- Cadence Cerebrus Intelligent Chip Explorer
- Innovus Block Implementation with Stylus Common UI
- Innovus Clock Concurrent Optimization Technology for Clock Tree Synthesis
- Innovus Clock Concurrent Optimization Technology with Stylus Common UI
- Innovus Hierarchical Implementation with Stylus Common UI
- Innovus Implementation System (Block)
- Innovus Implementation System (Hierarchical)
- Innovus Low-Power Flow with Stylus Common UI
- Low-Power Flow with Innovus Implementation System
- Virtuoso Digital Implementation
Synthesis and Test- ATPG Flow with Modus DFT Software Solution
- Advanced Synthesis with Genus Stylus Common UI
- Design for Test Fundamentals
- Fundamentals of IEEE 1801 Low-Power Specification Format
- Genus Low-Power Synthesis Flow with IEEE 1801
- Genus Physical Synthesis Flow
- Genus Synthesis Solution with Stylus Common UI
- Joules Power Calculator
- Low-Power Synthesis Flow with Genus Stylus Common UI
- Test Synthesis with Genus Stylus Common UI
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IC Package
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Languages and Methodologies
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Mixed-Signal Design Modeling, Simulation and Verification
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Onboarding Curricula
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PCB Design
Design Authoring- Allegro X Design Entry HDL Basics
- Allegro X Design Entry HDL Front-to-Back Flow
- Allegro X Design Entry HDL SKILL Programming Language
- Allegro X EDM Design Entry HDL Front-to-Back Flow
- Allegro X System Capture Basics
- Allegro X System Capture Front-to-Back Flow
- OrCAD X CIS
- OrCAD X Capture
- OrCAD X Capture Constraint Manager PCB Flow Basics
PCB Layout- Advanced Design Verification with the RAVEL Programming Language
- Allegro DesignTrue DFM
- Allegro X High-Speed Constraint Management
- Allegro X PCB Editor Advanced Methodologies
- Allegro X PCB Editor Basic Techniques
- Allegro X PCB Editor Intermediate Techniques
- Allegro X PCB Editor SKILL Programming Language
- Allegro X PCB Router Basics
- Allegro X RF PCB
- Allegro X Update Training
- OrCAD X Presto Basic Techniques
SI/PI Analysis Point Tools- Celsius Thermal Solver
- Clarity 3D Solver
- DC and Thermal Analysis with Celsius PowerDC
- Essential High-Speed PCB Design for Signal Integrity
- Model Generation and Analysis using PowerSI and Broadband SPICE
- PDN and Voltage Ripple Analysis with Sigrity X OptimizePI and SystemPI
- Sigrity Aurora
- Sigrity PowerDC and OptimizePI
- Sigrity PowerDC and OptimizePI (Français)
- Sigrity SystemSI for Parallel Bus and Serial Link Analysis
- SystemSI for Parallel Bus and Serial Link Analysis
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Reality DC
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System Design and Verification
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Tensilica Processor IP
Tensilica Processors- Tensilica Instruction Extension Language and Design
- Tensilica System Modeling using XTSC
- Tensilica Xtensa LX Hardware Verification and EDA
- Tensilica Xtensa LX Processor Fundamentals
- Tensilica Xtensa LX Processor Interfaces
- Tensilica Xtensa NX Hardware Verification and EDA
- Tensilica Xtensa NX Processor Fundamentals
- Tensilica Xtensa NX Processor Interfaces
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Academic Curricula
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Tech Domain Certification Programs
