The TripleCheck™ IP Validator helps IP developers verify that their designs comply with the specifications that define standard interfaces. TripleCheck works in conjunction with the Cadence Verification IP (VIP) Catalog to simplify and accelerate compliance testing and interface verification by providing the three things that verification engineers need most: Automatic configuration and customization of the test suite, Coverage and vPlan based on the user's configuration file.

TripleCheck Test Suite diagram

Customized testsuite to boost your IP verification based on your specific VIP configuration

Comprehensive and Robust Test suite for Early and Fast Verification

The test suite is ready to use, and includes spec-driven tests. It includes both directed and constrained-random sequences, reaching 100% of the verification plan out of the box. It is filtered and customized automatically per the configuration file. The test suite is a superset of post-silicon compliance tests.

Functional Coverage Model

The native SystemVerilog coverage database supports all simulators, covers all spec features, and is filtered based on the configuration specified. Thus, it provides complete coverage of your configuration.

Verification plan for Transparent Execution

The verification Plan (vPlan) is an executed document that is layered on the protocol specification. The vPlan provides meaningful verification objectives for each protocol and is linked to the native SV coverage database. It is automatically filtered to match DUT-specific configuration and is integrated with Incisive.