Best-in-class PCI Express® Verification IP for your IP, SoC, and system-level design testing.
Used by all leading PCIe, IP, and SoC design verification teams for all generations.
The Cadence® Verification IP (VIP) for PCI Express® (PCIe®) provides a complete bus functional model (BFM) with thousands of integrated automatic protocol checks for all three protocol layers (TL, DLL, PL) in addition to specific PIPE and PIE. Designed for easy integration in testbenches at IP, SoC, and system levels, the VIP helps engineers reduce time to first test, accelerate verification closure, and ensure end-product quality.
The VIP for PCIe can be used as a standalone, as a platform for running TripleCheck tests, and\or for enabling SR-IOV, MR-IOV, CXL, NVMe or CCIX on top of the base VIP. The VIP for PCIe supports a wide range of verification platforms, all major simulators, and the industry-standard Universal Verification Methodology (UVM). The VIP core is written in native C language for excellent performance, with seamless integration with all verification languages—SystemVerilog, e, Verilog, VHDL, and SystemC®.
Supported specification: PCI Express specification versions 6.0, 5.0, 4.0, 3.0, 2.1, 2.0, and 1.1, latest ECNs, Intel PIPE, Single-Root I/O Virtualization and Sharing Specification Revision 1.1 and Multi-Root I/O Virtualization and Sharing Specification Revision 1.0.
Product Highlights
Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
Over 40 common built-in/predefined error injection scenarios
Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation
Dynamic activation to enable setting the VIP as active/passive during run time
Packet tracker creation for easy debugging
Provides extensive coverage in e and SystemVerilog
Key Features
The following table describes key features from the specifications that are implemented in the VIP:
Feature Name
Description
Device Type
Root Complex, End Point, Legacy End Point, Switch, PHY DUT, Bridge
