Best-in-class PCI Express® Verification IP for your IP, SoC, and system-level design testing.

Used by all leading PCIe, IP, and SoC design verification teams for all generations.

The Cadence® Verification IP (VIP) for PCI Express® (PCIe®) provides a complete bus functional model (BFM) with thousands of integrated automatic protocol checks for all three protocol layers (TL, DLL, PL) in addition to specific PIPE and PIE. Designed for easy integration in testbenches at IP, SoC, and system levels, the VIP helps engineers reduce time to first test, accelerate verification closure, and ensure end-product quality.

The VIP for PCIe can be used as a standalone, as a platform for running TripleCheck tests, and\or for enabling SR-IOV, MR-IOV, CXL, NVMe or CCIX on top of the base VIP. The VIP for PCIe supports a wide range of verification platforms, all major simulators, and the industry-standard Universal Verification Methodology (UVM). The VIP core is written in native C language for excellent performance, with seamless integration with all verification languages—SystemVerilog, e, Verilog, VHDL, and SystemC®.

Supported specification: PCI Express specification versions 6.0, 5.0, 4.0, 3.0, 2.1, 2.0, and 1.1, latest ECNs, Intel PIPE, Single-Root I/O Virtualization and Sharing Specification Revision 1.1 and Multi-Root I/O Virtualization and Sharing Specification Revision 1.0.

PCIe diagram

Product Highlights

  • Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
  • Over 40 common built-in/predefined error injection scenarios
  • Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation
  • Dynamic activation to enable setting the VIP as active/passive during run time
  • Packet tracker creation for easy debugging
  • Provides extensive coverage in e and SystemVerilog

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name


Device Type

  • Root Complex, End Point, Legacy End Point, Switch, PHY DUT, Bridge


  • Serial, Parallel (8-bit, 10-bit, 128-bit, and 130-bit), PIE8, PIPE 3.0, PIPE 4.0, PIPE 4.3, PIPE 4.4.x, PIPE 5.x, PIPE 6.0

Link Rate

  • Supports all PCIe speeds: 2.5GT/s, 5.0GT/s, 8.0GT/s, 16GT/s, 32.0GT/s, 64GT/s

Link Width

  • Configurable link width support x1, x2, x4, x8, x16, x32
  • Full support for up and down configuration

PIPE Support

  • PIPE 3.0, PIPE 4.0, PIPE 4.3, PIPE 4.4.x, PIPE 5.x, PIPE 6.0
  • SerDes mode
  • RxValid synchronous to RxCLK in SerDes mode
  • Loopback updates including equalization bypass (for lanes under test)

PAM-4 Signaling

  • PAM-4 signaling at 64GT/s


  • Forward Error Correction

Virtual Channel

  • Automatic or user-defined flow control initialization per virtual channel

Side-Band Signal Support


Protocol Timers

  • Full configuration capability
  • ACK, NAK, Replay timer simplification for Gen 4.0

Fault Isolation

  • Advanced error reporting (AER) to assist in fault isolation and root cause analysis


  • Perform and control all equalization flow for all PCIe generations

FLIT support

  • FLIT support for Gen6 and beyond
  • CRC detection in FLITS
  • FLIT mode TLP header, DLLP, NOP, NOP2
  • 8b/10b FLIT mode
  • 128b/130 bit FLIT mode

Flow Control Credit (FCC)

  • Full control of flow control credits
  • Flow control scaling
  • Initial allocation of FCCs
  • Dynamic FCC updates

Retimer Support

  • Root Complex and End Point support for recognizing retimer in the topology

Tag Scaling

  • Extended tag support to increase number of outstanding non-posted requests

RX Margining

  • Lane margining at receiver for 16GT/s and beyond

Clock Compensation

  • Clock compensation via addtion/removal of SKP OS

Elastic Buffer Mode

  • Ability to control the elasticity buffer operating mode: Nominal Half Full/Nominal Empty

Electrical Idle

  • Infer electrical idle condition for all PCIe generations

Hierarchy Enumeration

  • Provides a complete PCIe protocol hierarchy enumeration process including resource allocation


  • Complete link training status state machine modeling
  • Configuration states
  • Power saving states
  • Recovery states


  • Ability to insert skew between lanes

Clock Recovery

  • Clock recovery mechanisms supported:
  • Incoming bit stream
  • Reference clock

Clock Jitter

  • Ability to add jitter to clock

Address Space

  • Support for all types of address spaces:
  • Memory
  • I/O
  • Configuration
  • MSI and MSI-X


  • Predefined sequence number, link CRC, and duplicate TL error injections

Function Level Reset (FLR)

  • Full compliance


  • Handles interrupt mechanisms: MSI, MSI-X, INTx

Power Management

  • Full power management support: D-states, L-States, ASPM

ECN Support

  • Process Address Space ID (PASID)
  • PASID Translation
  • Alternative Routing-ID Interpretation (ARI)
  • Atomic Operations
  • Resizable BAR Capability
  • Multicast
  • Dynamic Power Allocation
  • ID-Based Ordering
  • Latency Tolerance Reporting (LTR)
  • Extended Tag Enable Default
  • TLP Processing Hints
  • TLP Prefix
  • Optimized Buffer Flush/FiIll (OBFF)
  • ASPM Option
  • End-End TLP Prefix Changes for RC
  • Protocol Multiplexing (PMUX)
  • Separate Refclk Independent SSC Architecture (SRIS)
  • Precision Time Measurement (PTM) Revision 1.0
  • L1 PM sub-state with CLKREQ
  • Designated Vendor-Specific Extended Capability (DVSEC)
  • Expanded Resizable BAR
  • VF Resizable BAR
  • Deferred Memory Write (DMWr) ECN
  • Integrity and Data Encryption (IDE) ECR
  • Data Object Exchange (DOE)
  • Component Measurement and Authentication (CMA)

PCIe 1.1, 2.0, 3.0

  • 128b/130b encoding
  • Injecting and checking framing tokens errors
  • DC Balance checks and coverage
  • Equalization procedure support, error injection, and checks

PCIe 4.0

  • Operates at 16 GT/s
  • Multi-Lane RX Error reporting per lane in the Lane Error Status register
  • Tag Scaling
  • Flow Control Scaling
  • RX Margining

PCIe 5.0

  • Equalization updates including equalization bypass capability
  • Precoding support
  • Polling Compliance updates

PCIe 6.0

  • PAM-4 Signaling at 64GT/s
  • FLIT support
  • 1b/1b encoding
  • Forward error correction (FEC)
  • Gray coding
  • Precoding updates


  • EROM
  • Per VF function level reset
  • VF Migration
  • Alternate routine ID (ARI)
  • VF sharing header log files


  • Virtual link (VL) = 0
  • TLP prefix tagging generation
  • Per VH reset
  • Message processing (IntX/PM)
  • Base error detection and logging
  • MRA switch Hot Plug
  • Congestion management

Simulation Test Suite

Extensive testsuite, coverage model and verification plan with clear linkage to the specification for simple and fast compliance testing.

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