Overview
Best-in-class TileLink Verification IP (VIP) or your IP, SoC, and system-level design testing.
This Cadence® Verification IP (VIP) provides support for the TileLink specification. It provides a highly capable compliance verification solution simulation, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for TileLink runs on all leading simulators. It supports user interfaces in SV-UVM, plain SV, and C. The VIP includes a bus functional model (BFM) with automatic protocol checkers, supports random stimuli, and collects functional coverage. Cadence provides an integrated solution for interconnect verification that supports the verification of coherent interconnect and performance analysis that provides automated generation of testbenches. The VIP provides a framework for system-level coherency, integrated automatic protocol checks and coverage model.
Product Highlights
Key Features
The following table describes key features from the specifications that are implemented in the VIP:
Feature Name |
Description |
|---|---|
Channels |
|
TL-UL |
|
TL-UH |
|
TL-C |
|
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