Overview
Best-in-class SPDIF Verification IP for your IP, SoC, and system-level design testing.
Incorporating the latest protocol updates, the mature and comprehensive Cadence® Verification IP (VIP) for the SPDIF protocol provides a complete bus functional model (BFM), integrated automatic protocol checks, coverage model, and compliance tests. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for SPDIF helps you reduce time to test, accelerate verification closure, and ensure end-product quality. Our VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).
Supported Specification: Indian Standard DIGITAL AUDIO INTERFACE PART 3 CONSUMER APPLICATIONS (IEC 60958-1)
Product Highlights
Key Features
The following table describes key features from the specifications that are implemented in the VIP:
Feature Name |
Description |
|---|---|
Maximum Audio Sample Word Length |
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Audio Sample Word Length |
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Parity Generation |
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Preamble Error Injection |
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