Best in class MIPI® UniPro Verification IP for your IP, SoC, and system-level design testing.

In production since 2011 on dozens of production designs.

Incorporating the latest protocol updates, the mature and comprehensive Cadence® Verification IP (VIP) for the MIPI ® UniProsm Protocol provides a complete bus functional model (BFM), integrated automatic protocol checks, coverage model, and compliance tests. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for UniPro helps you reduce time to test, accelerate verification closure, and ensure end-product quality. Our VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported Specifications: MIPI UniPro v1.6, v1.8 and v2.0 and M-PHY v4.0, v4.1, and v5.0.

MIPI UniPro diagram

Product Highlights

  • Compliance: Contains predefined checks to verify that the DUT agents adhere to the protocol rules

  • Error Detection: Supports error detection on all layers, more than 200 different protocol checks.
  • Coverage: Monitors, checks, and collects coverage on bus traffic using hundreds of automatic protocol checks, including configuration and runtime checks.

  • Error Injection: Random and pre-defined error injections promote easy testing of scenarios and scenario creations.

  • Environment Setup: Configurable environment layers allow for early and specified verification of Data Link Layer.

  • Traffic: Generates UniPro traffic on both transaction classes for master and slave and supports constrained-random bus traffic generation.

  • Packet tracker creation for easy debugging
  • Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation

  • Dynamic activation to enable setting the VIP as active/passive during run time

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name

Description

Serial and RMMI Interfaces

  • Supports Serial and RMMI interfaces (downstream)

CPort Signal Interface

  • Supports CPort signal interface (upstream)

All Layers Supported

  • Supports PHY Adapter, Data Link, Network, and Transport layers

Built-In Sequences

  • PA link start up, (re-)initialization, configuration, error-recovery, and hibernate enter/exit sequences

Data Link Layer

  • Supports DLL initialization, TC0 and TC1, flow control, and acknowledgment mechanisms

Transport Layer

  • Supports TL connection management and addressing, segmentation and reassembly,
    end-to-end flow control, and multi-CPort arbitration

Lane Capabilities

  • Supports up to four lanes, PWM G1-G7, HS G1-G5 in each direction, and A/B HS rate series

Connectivity Capabilities

  • Supports testing of 1.6, 1.61, 1.8, and 2.0 connection compatibility

PHY Testing

  • Complete support of test mode

Test Feature

  • Supports complete test feature functionality

CDR

  • Supports Clock Data Recovery

Simulation Test Suite

Extensive testsuite, coverage model and verification plan with clear linkage to the specification for simple and fast compliance testing.

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