Overview

MIPI® SPMIsm Verification IP for Your IP, SoC, and System-level Design Testing

Cadence provides a mature and comprehensive Verification IP (VIP) for the MIPI® SPMIsm (System Power Management Interface) protocol. Incorporating the latest protocol updates, the Cadence Verification IP for SPMI provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for SPMI helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP runs on all major simulators and supports SystemVerilog language along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported specification: MIPI specifications for SPMI v1.0 and v2.0.

MIPI SPMI diagram

Product Highlights

  • Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
  • Generates constrained-random bus traffic with predefined error injection
  • Callbacks access at multiple queue points for scoreboarding and data manipulation
  • Packet tracker creation for easy debugging
  • Dynamic activation to enable setting the VIP as active/passive during run time
  • Provides extensive coverage in SystemVerilog

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name

Description

Topology
  • Multiple subordinates and multiple mains topology

Clock
  • High-speed and low-speed device classes

Main connection
  • Main connection by Detection of SSC, Bus Idle, Bus arbitration

Main arbitration
  • Main priority and secondary arbitration requests

Subordinate types
  • RCS and NRCS subordinates

Sl arbitration
  • Supports A-bit and SR-bit subordinate arbitration requests

Packet generation
  • Command, address, data, no response frame, and SPMI commands

Device address types
  • Supports MID, GSID, and USID device addresses

ACK/NACK
  • ACK/NACK mechanism as per version 2.0 specification

Arbitration generation
  • Capability to generate simultaneous arbitration request scenario

Error Injection
  • Injection/detection of errors for example parity errors/noise spike at different arbitration level

SSC
  • Generation and detection of SSC (Sequence Start Condition)

Event Notification
  • Arbitration win/lost, error detection, command/data/address frame sent, and subordinate A/SR bit eligibility status

Simulation Test Suite

Comprehensive test suite with coverage model for simple and fast design and verification bring-up.

RapidCheck Test Suite

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