Best in class MIPI® SLIMbus Verification IP for your IP, SoC, and system-level design testing.

Cadence provides a mature and comprehensive Verification IP (VIP) for the SLIMbus protocol, which is part of the MIPI family. Incorporating the latest protocol updates, the SLIMbus VIP provides a complete bus functional model (BFM), integrated automatic protocol checks, coverage model, and compliance tests. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, Cadence SLIMbus VIP helps you reduce time to test, accelerate verification closure, and ensure end-product quality. Our VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported Specifications: MIPI SLIMbus Specification version 1.3 and version 2.0.

MIPI SLIMbus diagram

Product Highlights

  • Compliance: Contains predefined checks to verify that the DUT components and devices adhere to the protocol rules
  • Coverage: Monitors, checks, and collects coverage on bus traffic, transport protocols and messages
  • Random error injection promotes easy testing of scenarios
  • Transaction tracker Configurable tracking of all the transactions on the channels

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name

Description

Segment distribution

  • SLIMbus v2.0: Supports all segment distribution codes.

Multichannel stream

  • SLIMbus v2.0: Supports data carrying on multiple channels that have the same direction and sample rate and that are phase-aligned.

Multiline operation

  • Supports up to 8 data lines.

Transmits and receives all message types

  • Supports all protocol messages.

Transport protocols

  • isochronous, pushed, pulled, async simplex, async half-duplex, extended async simplex, and extended async half-duplex

Bus reconfiguration, and bus synchronization

  • Supports component boot-up sequence and recovery of sync loss.

Root frequency and clock gear

  • Provides ability to change root frequency and clock gear

Information/value elements

  • Supports information/value element messages

Full reset flow

  • Supports all kinds of protocol resets

Active framer

  • Supports all roles of active framer (framing channel and clocks)

Active framer handover

  • Supports the active framer handover flow

Clock pause

  • Supports clock pause flows

Simulation Test Suite

VIP comes along with a testsuite of scenarios for easy VIP evaluation and deployment.

Please contact us for further information.

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