Overview

Best in Class MIPI® I3Csm Verification IP for your IP, SoC, and System-level Design Testing

In production since 2015 on dozens of production design.

The Cadence Verification IP (VIP) for MIPI® I3Csm VIP provides support for the MIPI I3C protocol specification. It provides a mature, highly capable compliance verification solution that supports simulation, protocol checking, coverage collection, and analysis, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for I3C helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

MIPI I#C

Product Highlights

  • Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
  • Contains predefined checks to verify that the DUT agents adhere to the supported protocol features
  • Generates I3C traffic as single or multi-agent driving with the ability for constrained-random bus traffic
  • Provides ability to generate intentionally erroneous traffic on the bus
  • Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation
  • Packet tracker creation for easy debugging
  • Provides extensive coverage in e and SystemVerilog

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name

Description

I3C SDR mode
  • SDR private read/write data transfers

I3C HDR-DDR mode
  • HDR-DDR enter and exit patterns, command coding, bus turnaround, DDR flow control elements, and error detection

I3C HDR-ternary modes
  • Supports HDR-TSP and HDR-TSL modes including Data Transfer Ending Procedure Control (ENDXFER) and Ternary Flow Control Elements

I2C legacy mode
  • Supports I2C-only mode to simulate the I2C protocol as defined in the I2C specification

I3C CCC
  • Mandatory and optional CCCs: Direct and broadcast commands

Secondary controller
  • Supports processing secondary controller role requests

Target agents
  • Supports any number of I3C and I2C targets up to the limit of the specification

In-band interrupt
  • Supports processing of in-band Interrupts from I3C targets

In-band hard reset
  • Supports processing of in-band hard reset

Arbitration
  • Supports I3C address arbitration

Hot join
  • Supports hot-join procedure for adding targets to the bus on the fly

Dynamic address assignment
  • Supports the mandatory dynamic address assignment mode including SETDASA, SETAASA (v1.01 feature).

SDR error detection and recovery
  • Supports SDR error detection and recovery methods for I3C controller and I3C target devices, including S0 error detection and S0/S1 error recovery mechanism

Target response control
  • Implements user control of target response fields such as data, target busy, target sending NACK, etc.

I2C 50ns glitch filter
  • Supports optional 50ns glitch filter for I2C devices

I2C clock stretching
  • Supports I2C stretching

I2C start byte
  • Sending of optional start byte in transactions is available

I2C speed modes
  • Standard, fast, fast plus, ultra fast, and high-speed

I2C 7-bit/10-bit addressing
  • Configurable option to use for target addressing

I2C multi manager
  • Supports I2C multi manager feature

Group addressing
  • Supports this feature where the controller can send transaction on multiple targets at the same time using group addressing

Target reset
  • Supports new target reset pattern introduce in V1.1

Monitoring device early termination capability
  • Supports feature where target which is not participating in transaction can terminate the transaction

Device to device tunneling
  • Supports target to target transfer

HDR bulk transport mode
  • Supports HDR BT Mode where bulk transfer of data can be done

Multi lane data transfer
  • Supports multi lane for SDR, HDR DDR, HDR BT modes, and multi lane for HDR TSP is under development

Simulation Test Suite

Extensive test suite, coverage model, and verification plan with clear linkage to the specification for simple and fast compliance testing.

TripleCheck Test Suite

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