Cadence's best-in-class Verification IP (VIP) for MIPI® CSI-2sm for IP, SoCs and, system-level design testing.
In production since 2008 on dozens of production designs.
Cadence provides a mature and comprehensive VIP for the CSI-2 protocol, which is part of the MIPI family. Incorporating the latest protocol updates, the Cadence® VIP for CSI-2 provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for CSI-2 helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).
Generic Long Packet Data Types 1 to 4, user-defined format 1 to 8, Blanking Data, Null Packet, and Embedded Data
FS-FE, LS-LE, and all Generic Short Packet Codes (1 to 8)
Clock
Supports continuous and non-continuous TxWordClkHS and RxWordClkHS clock operation
Interleaving
Supports virtual channel and data type interleaving
Virtual Channel Extension
Supports up to 32 virtual channels over C-PHY and 16 virtual channels over D-PHY
Ultra-Low Power Mode (ULPM)
Supports Ultra-Low-Power mode (ULPM) on clock and data lanes
Triggers
Supports all 4 trigger commands, including low-power data after trigger transmission and low-power data pause
Pixel Layer
Supports pixel layer for RGB, RAW, and YUV422 data types
Supports pixel-to-byte packing
Scrambling
Supports lane-based data payload scrambling
Supports LFSR initialization for both D-PHY and C-PHY
Supports multiple sync word types insertion for C-PHY scrambling LFSR initialization
Latency Reduction Transport Efficiency (LRTE)
Supports merging multiple packets from the same frame in a single HS burst with protocol generated and consumed fillers and spacers over C-PHY and D-PHY
Efficient Packet Delimiter (EPD)
Supports PHY-generated and -consumed PDQ for both C-PHY and D-PHY
PDQ for D-PHY is HS-IDLE, and for C-PHY is sync words, when merging multiple packets with LRTE
Alternate Calibration Sequence for D-PHY
Supports PRBS9 generation of D-PHY Alternate Calibration Sequence includes updates of D-PHY v2.1 errata01
Frame Synchronization Packets
Supports increment of frame number by 1 or 2 for every FS Packet
Spacer Byte Generation
Supports to redefine spacers as a minimum value, as defined in the CSI2 v2.1 specification
End of Transmission packet (EoTp)
Supports a short packet after the last packet to indicate end of HS burst transmission
Spacers Generation
Supports spacers in the packet without PDQ(Packet Delimiter Quick) for CPHY and DPHY EPD option 1 and variable-length spacers for DPHY EPD option 2
Smart Region of Interest
Supports SEDP Packet and SROI packet option 1 and 2
Unified Serial Link
Supports SNS- and APP-initiated USL transactions in HS/LPDT mode and transport integrity checks
Supports USL BTA switch registers
Supports switching to soft standby and streaming mode
Supports Dynamic clock control
CSI-2 Over DPHY v2.5
ALP Mode - Support of Data transmission and all ALP control bursts
Fast Lane BTA - Burst Turn Around in ALP Mode
Clock Lane ULPS in ALP mode
CSI-2 Over CPHY v2.0
Fast Lane BTA - Burst Turn Around in ALP Mode
CSI2 over A-PHY v1.0
Supports CSI2 packet transfer over A-PHY serial and APPI interface
Camera Service Extension (CSE)
Supports SEP format over A/D/C-PHY
Protocol Adaptation Layer (PAL)
Supports all modes of TU function
Supports Multiple short packets in single A-Packet
