Gold standard for JEDEC® DDR4 NVDIMM-P memory device for your IP, SoC, and system-level design verification.

First to market with full DDR4 NVDIMM-P support.

This Cadence® Verification IP (VIP) supports the JEDEC® DDR4 NVDIMM-P memory device standard. It provides a mature, highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The DDR4 NVDIMM-P VIP is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.

DDR4 NVDIMM-P is the next generation DIMM specification that supports high capacity memory and block storage and extended memory address space.

Supported specification: JEDEC DDR4 NDIMM-P Specification.

DDR4 NVDIMM-P diagram

Product Highlights

  • Hundreds of protocol and timing checkers to easily catch design bugs
  • Multiple predefined configurations based on specific memory vendors' part numbers, datasheets, or generic JEDEC definitions available on
  • Transaction and memory callbacks for all protocol, model states, and device memory events
  • Ability to optionally skip initializations or dynamically change configuration parameters
  • Enables dynamically change of timing parameters during simulation
  • Extensive functional coverage in SystemVerilog
  • Support testbench language interfaces for SystemVerilog, UVM, OVM, and SystemC

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name


DRAM Compatible Pin Interface

  • Works with the same set of Pins as DDR4 UDIMM, RDIMM, and LRDIMM

Extended Memory Address Space

  • Supports up to 8TB memory

Handshaking Scheme

  • Supports Read and Write functionality with handshaking scheme between the Host controller and the Media controller

On-chip Commands

  • Supports on-chip ECC, XREAD and XWRITE, SREAD, SEND, SEND-W_PER, PWRITE, MRS, FLUSH, Power Down Entry and Exit, and ZQ Calibration Commands

Out-of-order Operation

  • DDR4 NVDIMM-P supports out of order memory Reads and Writes

Data Poison

  • Supports poison bit to indicate data corruption

DDR4 DB Integration

  • Reads and Writes will be propagated using the DDR4 DB device with Media controller connected to the DRAM side of DDR4 DB Data Pins

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Simulation Test Suite

MM comes along with a rich testsuite of scenarios for easy MM evaluation and deployment.

Please contact us for further information.