Gold standard for JEDEC® xSPI memory device for your IP, SoC, and system-level design verification.

xSPI in production since 2019 for many production designs.

The Cadence® Memory Model Verification IP (VIP) for xSPI provides verification of xSPI (Expanded SPI) NOR flash devices using the SPI protocol. The VIP for xSPI is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model. The VIP for xSPI includes both support for xSPI and VIP for OSPI NOR.

Supported specification: JEDEC specifications: JESD251 Profile 1 v1.0, JESD251-A1, JESD252, and JESD216D and Memory Vendors specifications of ADESTO (DS_XP032_114G_122018), MICRON (tn1235_sfdp_mt35x Rev. B 10/18 EN - compliant to JESD216B ONLY), MACRONIX, (AN0726 Rev1 for MX66UM2G45G) and CYPRESS (002-18216, Rev:*M).

xSPI diagram

Product Highlights

  • Hundreds of protocol and timing checkers to easily catch design bugs
  • Hundreds of predefined configurations based on specific memory vendors part numbers datasheets or generic JEDEC definitions available on ememory.com
  • Transaction and memory callbacks for all protocol, model states, and device memory events
  • Error injection capability through user modification of transaction contents
  • Ability to check for errors and change error severity
  • Ability to dynamically change configuration parameters
  • Packet tracker creation for easy debugging
  • Support testbench language interfaces for SystemVerilog and UVM

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name

Description

xSPI Profile 1

  • SPI (Read Zero Latency), DUAL (1-1-2, 1-2-2), Quad (As per JESD251-A1), and Octal modes Data Rate: STR and DTR

Modes

  • SPI-STR (1S-1S-1S), QUAD-STR (4S-4S-4S), OCTAL-STR(8S-8S-8S), and OCTAL-DTR (8D-8D-8D) modes

Reset

  • Software Reset Feature: Soft reset with reset enable (0x66) and reset command (0x99) with return to default protocol mode

Modes Switching Commands

  • Supports Command to enter OCTAL(E8h), QPI(38h), and SPI(FFh) modes

Read modes

  • Supports Read for SFDP Headers, Parameter Headers, and Parameter DWORDS, Page Read, Read Fast Wrapped, and Set up Read Wrapped

Octal DTR mode

  • Command Extension Feature for Octal DTR mode (8D-8D-8D)

Program Operation

  • Byte and Page Program, Program Suspend and Resume command

Erase Operation

  • Chip Erase and Block Erase (4, 32, 64, and 256 KB), Erase Suspend and Resume command

Deep Power Down

  • Supports Deep Power Down feature

SCCR

  • Write status control register command to all register fields, volatile and nonvolatile offset address, register bits and Read status register

Addressing Capability

  • 3-byte and 4-byte address modes. Enter and Exit 4-byte mode

Shared Pin Feature

  • Shared IO3 Pin with Hold Pin and Shared IO3 Pin with Reset Pin

Simulation Test Suite

MM comes along with a rich testsuite of scenarios for easy MM evaluation and deployment.

Please contact us for further information.

Master your tools

Tutorials, Documentation, and Local Experts

Cadence Online Support

Increase your efficiency in using Cadence Verification IP with Online trainings, VIP Portal, application notes, and troubleshooting articles