Overview

Gold standard for JEDEC® UFS memory device for your IP, SoC, and system-level design verification.

In production since 2012 on multiple production designs.

This Cadence® Verification IP (VIP) supports the JEDEC Universal Flash Storage (UFS) standard. The VIP for UFS is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.

UFS diagram

Product Highlights

  • Full stack support with UniPro and M-PHY or UFS standalone support via CPort interface
  • Hundreds of protocol and timing checkers to easily catch design bugs
  • Transaction and memory callbacks for all protocol, model states, and device memory events
  • Error injection capability through user modification of transaction contents
  • Ability to check for errors and change error severity
  • Boot and initialization sequence support; can be skipped to save simulation time
  • Ability to dynamically change configuration parameters
  • Packet tracker creation for easy debugging

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name

Description

Interfaces
  • DPDN I/F and RMMI I/F when used with UniPro VIP. CPort signaling pin I/F and CPort message using transactions

UTP Layer - UPIUs
  • NOP IN, NOP OUT, Query Request/ Response, Task Management Request/ Response, Command, Response, Data Out, Data In

UCS Layer - SCSI Commands
  • READ (6, 10, 16), WRITE (6, 10, 16), Inquiry, Report LUNs, Read Capacity (10, 16), Test Unit Ready, Verify, Start Stop Unit, Mode Sense, Request Sense, Security Protocol In, Security Protocol Out, Send Diagnostic, Read Buffer, Write Buffer, Pre-Fetch (10, 16), Synchronize Cache (10, 16), Mode select, Unmap, and Format

UFS Protocol Features
  • Boot functionality
  • LUNS and W-LUNS supported
  • Interleaving of commands supported
  • Types of queue supported : Shared queue and Per-LUN queue

CPort Signaling Interface

As specified by UniPro Specification:

  • CPort connection to Device UniPro
  • Direct CPort connection to Host UniPro

Supported Use Cases
  • UFS standalone (Transaction mode or using CPort signaling interface)
  • Full-stack UFS (with UniPro+M-PHY over DPDN serial interface or with UniPro only over RMMI interface)

UFS 3.0 Support
  • Support for HS Gear 3 and 4, IID feature in Task Management request UPIUs, Device Health Descriptor

UFS 3.1 Support
  • HPB, WriteBooster Buffer, Deep Sleep Power Mode, Performance Throttling

UFS 4.0 Support
  • EHS and its usage in RPMB, OOO RTT and Data In transmission, HPB 2.0, ARPMB

Simulation Test Suite

MM has a rich test suite of scenarios for easy MM evaluation and deployment.

Please contact us for further information.

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