Gold standard for SD CARD memory device for your IP, SoC, and system-level design verification.

In production since 2012 for many production designs.

This Cadence® Verification IP (VIP) upgrades the SD CARD and SDIO verification platform with Ultra High Speed Type II (UHS-II) support defined in the UHS-II Addendum specification of Part 1 Physical Layer Specification Version 4.00. It allows seamless verification of legacy SD CARD and SDIO protocol (version 3.00 and below) and the latest UHS-II interface. The UHS-II interface allows access to traditional SD CARD and SDIO applications through the SD-TRAN layer and to the UHS-II memory space through the CM-TRAN layer. The VIP allows full-stack UHS-II interface verification (TRAN + LINK + PHY) through the serial interface and protocol IP verification (stripped of PHY) through PHY-LINK I/F defined in the specification.

Supported specification: Part 1 Physical Layer Specification Version 4.00 and Part 1 UHS-II Addendum Version 1.00.

SD CARD and SDIO diagram

Product Highlights

  • Hundreds of protocol and timing checkers to easily catch design bugs
  • Hundreds of predefined configurations based on specific memory vendors' part numbers, datasheets, or generic JEDEC definitions available on ememory.com
  • Transaction and memory callbacks for all protocol, model states, and device memory events
  • Error injection capability through user modification of transaction contents
  • Ability to check for errors and change error severity
  • Callback events for packets at entry/exit of LINK layer and Transaction layer on the receive and transmit sides
  • Callback events at PHY layer to monitor bus activity and to inject errors
  • Ability to dynamically change configuration parameters
  • Packet tracker creation for easy debugging
  • Support testbench language interfaces for SystemVerilog and UVM

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name

Description

Speed Range A and B

  • Default Speed Range A and faster Range B support

PHY-LINK I/F

  • Interface defined in Appendix-F allows verification of protocol IP independently

Half-duplex

  • Half-duplex (2L-HD) mode of operation that doubles data throughput

Data Bust Streaming

  • Allows multiple model instances to be connected using ring connection

Data Burst Retry

  • Data Burst Retry support through the simulation of recoverable error

Embedded Flash

  • Support of an embedded flash as defined in eSD specification

Area

  • Support of the boot area, user area, and other partition through CMD43 and

Fast Boot

  • Support of fast boot feature

Boot Code Loading

  • Boot code can be loaded from one of the model instances designated as boot device

Low Power Mode

  • Low Power Mode supported through configuration register setting

Simulation Test Suite

MM comes along with a rich testsuite of scenarios for easy MM evaluation and deployment.

Please contact us for further information.

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