Overview

Gold standard for JEDEC® OctaRam memory device for your IP, SoC, and system-level design verification. In production since 2018 for many production designs.

The Cadence Memory Model Verification IP (VIP) for OctaRam provides verification of OctaRam and PSRAM controller using the OctaRam Double Data Rate RAM and PSRAM protocol.  It provides a mature, highly capable compliance verification solution applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for OctaRam is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model. 

Supported specification: Features of the following vendors: Macronix, Micron, and APMemory. Micron uses the term PSRAM instead of OctaRam.

OctaRam diagram

Product Highlights

  • Dozens of protocol and timing checkers to easily catch design bugs
  • Dozens of predefined configurations based on specific memory vendors' part numbers, datasheets, or generic definitions available on ememory.com
  • Transaction and memory callbacks for all protocol, model states, and device memory events
  • Error injection capability through user modification of transaction contents
  • Ability to check for errors and change error severity
  • Ability to dynamically change configuration parameters
  • Packet tracker creation for easy debugging
  • Support testbench language interfaces for SystemVerilog and UVM

Key Features

The following table describes key features from the specification that are implemented in the OctaRam VIP:

Feature Name

Description

Memory Size
  • 16Mb to 512Mb

SPI and Quad-SPI Mode
  • Quad Entry: Switch mode of operation from SPI to QSPI
  • Quad Exit: Switch mode of operation from QSPI to SPI for 16Mb and 64Mb Memory

Reset
  • Supports Hardware RESETn Pin and Software Global Reset command for PSRAM Device

Power up Initialization
  • Supports power up initialization with RESET pin as well as Global Reset command

Read and Write
  • Supports Identification Register Read
  • Supports Memory Read and Write with Continuous and Wrapped Burst
  • Supports Sync Read and Write with Wrapped and Hybrid Burst
  • Supports Read and Write 64-byte Hybrid Wrapped Data for PSRAM
  • Supports Read, Fast Read, Quad Read, Write, Quad Write for
  • 16Mb and 64Mb devices in SPI mode without Wrapped Burst
  • 16Mb Wrapped Read in SPI and QSPI mode with Wrapped Burst
  • Supports x8 and x16 IO modes with Mode Register configuration
  • Supports Linear burst with RBX feature
  • Supports 16/32/64 byte wrap in x8 and 16/32/64/2K byte wrap in x16
  • Supports 16/32/64 byte hybrid wrap

Burst Length Toggle
  • Switch the Wrapped Length to 32 byte from any value set in Mode Register 0 in SPI and QSPI mode for 16Mb Memory

Preamble
  • Supports Preamble Bit Patter Read command

Power Down and Sleep
  • Supports Deep Power Down operation
  • Half Sleep Mode/Entry: Switch device In Ultra Low Power State

Simulation Test Suite

MM has a rich test suite of scenarios for easy MM evaluation and deployment.

Please contact us for further information.

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